公开(公告)号：US11538508B2

公开(公告)日：2022-12-27

申请号：US17137975

申请日：2020-12-30

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Matthew A. Prather ,  Brent Keeth ,  Frank F Ross ,  Daniel Benjamin Stewart ,  Randall J. Rooney

IPC: G11C7/10 ,  G11C7/22

Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

公开(公告)号：US20140217498A1

公开(公告)日：2014-08-07

申请号：US14247968

申请日：2014-04-08

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Darren V. Young ,  Kunal R. Parekh ,  Casey Smith

IPC: H01L29/423 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L21/823425 ,  H01L21/82345 ,  H01L29/407 ,  H01L29/66621 ,  H01L29/7831

Abstract: Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode.

Abstract translation: 与半导体器件一起使用的嵌入式晶体管器件可以包括具有多个功函数材料的栅电极，彼此电隔离并且被提供有两个或多个电压源的材料，或者在栅电极内产生二极管结的材料。

公开(公告)号：US12300349B2

公开(公告)日：2025-05-13

申请号：US18087328

申请日：2022-12-22

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Matthew A. Prather ,  Brent Keeth ,  Frank F Ross ,  Daniel Benjamin Stewart ,  Randall J. Rooney

IPC: G11C7/10 ,  G11C7/22

Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

公开(公告)号：US20230127970A1

公开(公告)日：2023-04-27

申请号：US18087328

申请日：2022-12-22

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Matthew A. Prather ,  Brent Keeth ,  Frank F. Ross ,  Daniel Benjamin Stewart ,  Randall J. Rooney

IPC: G11C7/10 ,  G11C7/22

Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

公开(公告)号：US09502516B2

公开(公告)日：2016-11-22

申请号：US14247968

申请日：2014-04-08

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Darren V. Young ,  Kunal R. Parekh ,  Casey Smith

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/40 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L21/823425 ,  H01L21/82345 ,  H01L29/407 ,  H01L29/66621 ,  H01L29/7831

Abstract: Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode.

Abstract translation: 与半导体器件一起使用的嵌入式晶体管器件可以包括具有多个功函数材料的栅电极，彼此电隔离并且被提供有两个或多个电压源的材料，或者在栅电极内产生二极管结的材料。

公开(公告)号：US20150014811A1

公开(公告)日：2015-01-15

申请号：US14499720

申请日：2014-09-29

Applicant: Micron Technology, Inc.

Inventor： Casey Smith ,  Jasper S. Gibbons ,  Kunal R. Parekh

IPC: H01L23/525 ,  H01L21/768

CPC classification number: H01L23/5252 ,  H01L21/76879 ,  H01L21/823425 ,  H01L21/82345 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Antifuses having two or more materials with differing work function values may be fabricated as recessed access devices and spherical recessed access devices for use with integrated circuit devices and semiconductor devices. The use of materials having different work function values in the fabrication of recessed access device antifuses allows the breakdown areas of the antifuse device to be customized or predicted.

Abstract translation: 具有两种或更多种具有不同功函数值的材料的防潮剂可以被制造为用于集成电路器件和半导体器件的凹陷入口器件和球形凹入入口器件。 在制造嵌入式接入装置反熔丝中使用具有不同功函数的材料允许定制或预测反熔丝装置的击穿面积。