公开(公告)号：US12300349B2

公开(公告)日：2025-05-13

申请号：US18087328

申请日：2022-12-22

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Matthew A. Prather ,  Brent Keeth ,  Frank F Ross ,  Daniel Benjamin Stewart ,  Randall J. Rooney

IPC: G11C7/10 ,  G11C7/22

Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

公开(公告)号：US20240256473A1

公开(公告)日：2024-08-01

申请号：US18630400

申请日：2024-04-09

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Frank F Ross ,  Richard C Murphy

IPC: G06F13/16 ,  G06N3/004 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06F13/1668 ,  G06N3/004 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.

公开(公告)号：US11538508B2

公开(公告)日：2022-12-27

申请号：US17137975

申请日：2020-12-30

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Matthew A. Prather ,  Brent Keeth ,  Frank F Ross ,  Daniel Benjamin Stewart ,  Randall J. Rooney

IPC: G11C7/10 ,  G11C7/22

Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

公开(公告)号：US11989141B2

公开(公告)日：2024-05-21

申请号：US17131217

申请日：2020-12-22

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Frank F Ross ,  Richard C Murphy

IPC: G06F13/16 ,  G06N3/004 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06F13/1668 ,  G06N3/004 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.

公开(公告)号：US11030132B2

公开(公告)日：2021-06-08

申请号：US16157900

申请日：2018-10-11

Applicant: Micron Technology, Inc.

Inventor： Paul Stonelake ,  Bryan T. Silbermann ,  Frank F Ross

IPC: G06F13/16 ,  G11C11/406 ,  G06F12/1009 ,  G06F13/42 ,  G06F12/02 ,  G06F13/20

Abstract: A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.