公开(公告)号：US20230317800A1

公开(公告)日：2023-10-05

申请号：US17712776

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Dhirendra Dhananjay Vaidya ,  Lei Wei ,  Gurpreet Lugani ,  Sumeet C. Pandey

IPC: H01L29/40 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L29/402 ,  H01L27/11556 ,  H01L27/11582

Abstract: Memory circuitry comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. The insulative tiers and the conductive tiers of the laterally-spaced memory blocks extend from a memory-array region into a stair-step region. Strings of memory cells comprise operative channel-material strings that extend through the insulative tiers and the conductive tiers in individual of the laterally-spaced memory blocks in the memory-array region. The operative channel-material strings directly electrically couple with conductor material of the conductor tier. The individual laterally-spaced memory blocks comprise an intermediate region between the operative channel-material strings and the stair-step region. A dummy through-array-via (TAV) extends through the insulative tiers and the conductive tiers in the intermediate region in the individual laterally-spaced memory blocks. The dummy TAV is directly electrically coupled with the operative channel-material strings in its memory block. Other embodiments are disclosed.