公开(公告)号：US20240428862A1

公开(公告)日：2024-12-26

申请号：US18748679

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Taehyun Kim ,  Brian Kwon ,  Dong Kyo Shim ,  Kwang Ho Kim ,  Erwin E. Yu ,  Fulvio Rori

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/34

Abstract: Control logic in a memory device initiates a program operation to program one or more memory cells of a first sub-block of a memory array, the program operation including a seeding phase. During the seeding phase, a first wordline voltage is caused to be applied to a first wordline segment associated with a first portion of the memory array. During the seeding phase, a second wordline voltage is caused to be applied to a second wordline segment associated with a second portion of the memory array, where the first wordline voltage and the second wordline voltage cause a seeding bias voltage to be applied to the first sub-block group and inhibit application of the seeding bias voltage to the second sub-block group.