公开(公告)号：US20240170075A1

公开(公告)日：2024-05-23

申请号：US18387217

申请日：2023-11-06

Applicant: Micron Technology, Inc.

Inventor： Kwang Ho Kim ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C16/24

Abstract: Entry of a memory device into a standby mode is determined. During the standby mode of the memory device, a first bias voltage level is caused to be applied to a sense amplifier latch of a sense amplifier of a page buffer circuit of the memory device. During the standby mode, a second bias voltage level is caused to be applied to a set of data latches of the sense amplifier of the page buffer circuit of the memory device, wherein the second bias voltage level is different from the first bias voltage level.

公开(公告)号：US20240428862A1

公开(公告)日：2024-12-26

申请号：US18748679

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Taehyun Kim ,  Brian Kwon ,  Dong Kyo Shim ,  Kwang Ho Kim ,  Erwin E. Yu ,  Fulvio Rori

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/34

Abstract: Control logic in a memory device initiates a program operation to program one or more memory cells of a first sub-block of a memory array, the program operation including a seeding phase. During the seeding phase, a first wordline voltage is caused to be applied to a first wordline segment associated with a first portion of the memory array. During the seeding phase, a second wordline voltage is caused to be applied to a second wordline segment associated with a second portion of the memory array, where the first wordline voltage and the second wordline voltage cause a seeding bias voltage to be applied to the first sub-block group and inhibit application of the seeding bias voltage to the second sub-block group.