公开(公告)号：US20160189763A1

公开(公告)日：2016-06-30

申请号：US15063140

申请日：2016-03-07

Applicant: Micron Technology, Inc.

Inventor： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

IPC: G11C11/4076

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

Abstract translation: 公开了系统，装置和方法。 在一种这样的方法的实施例中，一种对接收到的命令信号进行解码的方法，该方法包括将接收的命令信号与在时钟信号的第一时钟沿提供给存储器地址节点的信号相结合地解码，以产生多个存储器 控制信号。 接收到的命令信号与在时钟信号的第一时钟沿提供给存储器地址节点的信号相结合表示存储器命令。 此外，在时钟信号的第二时钟沿提供给存储器地址节点的信号不与所接收的命令信号组合解码。 存储器命令可以是减少功率命令和/或无操作命令。

公开(公告)号：US10127969B2

公开(公告)日：2018-11-13

申请号：US15456164

申请日：2017-03-10

Applicant: Micron Technology, Inc.

Inventor： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

IPC: G11C11/4076 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408

Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

公开(公告)号：US20170186475A1

公开(公告)日：2017-06-29

申请号：US15456164

申请日：2017-03-10

Applicant: Micron Technology, Inc.

Inventor： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

IPC: G11C11/4076 ,  G11C11/406 ,  G11C11/408 ,  G06F3/06

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

公开(公告)号：US09633713B2

公开(公告)日：2017-04-25

申请号：US15063140

申请日：2016-03-07

Applicant: Micron Technology, Inc.

Inventor： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

IPC: G11C5/14 ,  G11C7/00 ,  G11C8/00 ,  G11C11/4076 ,  G11C7/10 ,  G11C8/18 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

Abstract: Methods are disclosed. In an embodiment of one such method, a method of receiving command signals, the method comprises receiving command signals in combination with a signal provided to a memory address node at a first clock edge and a second clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge and the second clock edge of the clock signal, represents memory commands.