公开(公告)号：US20240071464A1

公开(公告)日：2024-02-29

申请号：US17823450

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Erik T. Barmon ,  Yang Lu ,  Nathaniel J. Meier ,  Kang-Yong Kim

IPC: G11C11/408 ,  G11C7/24 ,  G11C29/18 ,  G11C29/56

CPC classification number: G11C11/408 ,  G11C7/24 ,  G11C29/18 ,  G11C29/56004

Abstract: Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.