公开(公告)号：US10651315B2

公开(公告)日：2020-05-12

申请号：US13716287

申请日：2012-12-17

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/225 ,  H01L27/11556 ,  H01L29/788 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/11519 ,  H01L23/528 ,  H01L23/532 ,  H01L27/1157 ,  H01L21/285 ,  H01L23/535 ,  H01L29/66 ,  H01L29/792

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.