公开(公告)号：US20030132428A1

公开(公告)日：2003-07-17

申请号：US10053300

申请日：2002-01-17

Applicant: Micron Technology, Inc.

Inventor： Vishnu K. Agarwal ,  Fred Fishburn ,  Rongsheng Yang ,  Howard E. Rhodes ,  Jeffrey A. McKee

IPC: H01L047/00

CPC classification number: H01L21/823481 ,  H01L21/76232

Abstract: Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposited thereon, defines the process stack. The dopant is selected having the same n- or p-typing as the substrate. Through etching, the first and second layers of the process stack become pulled back from a trench wall of the substrate to form the implant region. Occupation of the implant region by the dopant prevents undesirable transistor leakage because the electrical characteristics of the implant region are so significantly changed, in comparison to central areas of the substrate underneath the first layer, that the threshold voltage of the implant region is raised to be about equivalent to or greater than the substantially uniform threshold voltage in the central area.

Abstract translation: 在具有通过拉回工艺叠层的第一层和第二层而形成的掺杂注入区的衬底中，晶体管结构中不期望的晶体管泄漏变得大大降低。 衬底的一部分也具有沉积在其上的第一和第二层，限定了工艺叠层。 掺杂剂选择具有与底物相同的n-或p-型。 通过蚀刻，工艺堆叠的第一和第二层从衬底的沟槽壁拉回以形成植入区域。 由掺杂剂对植入区域的占用防止了不期望的晶体管泄漏，因为与第一层下方的衬底的中心区域相比，注入区域的电特性如此显着地改变，使植入区域的阈值电压升高到 约等于或大于中心区域中的基本均匀的阈值电压。

公开(公告)号：US20030164513A1

公开(公告)日：2003-09-04

申请号：US10379494

申请日：2003-03-04

Applicant: Micron Technology, Inc.

Inventor： Er-Xuan Ping ,  Jeffrey A. McKee

IPC: H01L029/76

CPC classification number: H01L29/66666 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28562 ,  H01L27/10873 ,  H01L27/10876 ,  H01L29/66628 ,  H01L29/66787 ,  H01L29/66893 ,  H01L29/7834 ,  H01L29/78642

Abstract: Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of monocrystalline silicon on the surface of a semiconductive substrate, and forming a thin film of insulative material over the epitaxial layer. A portion of the insulative layer is removed to expose the top surface of the epitaxial layer, with the insulative material remaining along the sidewalls as spacers to prevent lateral growth. A second epitaxial layer is selectively grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface. The resultant structure can function, for example, as a vertical gate of a DRAM cell, elevated source/drain structures, or other semiconductor device feature.