公开(公告)号：US20240291492A1

公开(公告)日：2024-08-29

申请号：US18507314

申请日：2023-11-13

Applicant: Micron Technology, Inc.

Inventor： Jinha Hwang

IPC: H03K19/0185 ,  H03F3/45 ,  H03K3/012 ,  H03K3/356

CPC classification number: H03K19/018528 ,  H03F3/45183 ,  H03K3/012 ,  H03K3/35613

Abstract: A semiconductor device includes a first sensing stage configured to sense a voltage differential of a data signal and a reference signal and output a first amplified voltage differential, wherein the first amplified voltage differential includes a first voltage at a first output node and a second voltage at a second output node. The semiconductor device further includes a second sensing stage configured to sense the first amplified voltage differential and output a second amplified voltage differential, where the second amplified voltage differential includes a third voltage at a third output node and a fourth voltage at a fourth output node. A first power gating circuit is coupled to the third output node and a second power gating circuit is coupled to the fourth output node.

公开(公告)号：US20240249766A1

公开(公告)日：2024-07-25

申请号：US18506208

申请日：2023-11-10

Applicant: Micron Technology, Inc.

Inventor： Jinha Hwang ,  Won Joo Yun

IPC: G11C11/4091 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G11C11/4091 ,  G11C11/4076 ,  G11C11/4093

Abstract: A semiconductor device includes an interface configured to receive clock signals and data signals. The interface includes a dual-tail latch. The dual-tail latch includes a sensing stage configured to sense and to amplify a differential voltage between at least a portion of the data signals and another signal. The sensing stage includes a first node and a second node between which the amplified differential voltage is output from the sensing stage. The dual-tail latch also includes a latch stage configured to latch a first latched value and a second latched value based at least in part on the amplified differential voltage. Moreover, the differential voltage is based at least in part on a previous first value and a previous second value from the latch stage fed back to the sensing stage.