公开(公告)号：US20240248861A1

公开(公告)日：2024-07-25

申请号：US18506229

申请日：2023-11-10

申请人： Micron Technology, Inc.

发明人： Bhargav Kalva ,  Won Joo Yun

IPC分类号： G06F13/20

CPC分类号： G06F13/20 ,  G06F2213/0002

摘要： A semiconductor device includes a pair of transistors configured to implement buffering of input data to outputs. The semiconductor device also includes a first transistor configured to receive a common-mode of the outputs at a gate terminal of the first transistor. The semiconductor device also includes a current source configured to control a tail current from the pair of transistors. Additionally, the semiconductor device includes a second transistor configured to adjust the tail current based at least in part on changes in a reference voltage used by the pair of transistors to buffer the input data. Furthermore, the semiconductor device includes a third transistor configured to adjust the tail current based at least in part on changes in locally generated reference voltage based at least in part on a process and temperature variations.

公开(公告)号：US11789835B2

公开(公告)日：2023-10-17

申请号：US16953828

申请日：2020-11-20

申请人： Micron Technology, Inc.

发明人： Sang-Hoon Shin ,  Won Joo Yun ,  Rajesh H. Kariya

IPC分类号： G06F11/27 ,  G06F1/00 ,  G06F13/00 ,  G06F1/12 ,  G06F13/20

CPC分类号： G06F11/27 ,  G06F1/12 ,  G06F13/20

摘要： Test input/output speed conversion and related apparatuses and methods are disclosed. An apparatus includes a glue circuit and a BIST circuit for core circuitry of an integrated circuit device. The, the BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glue circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glue circuit is configured to convert between second speed test interface signals and second speed input/output signals operating at a second speed and first speed test interface signals and first speed input/output signals operating at the first speed. The second speed is different from the first speed.

公开(公告)号：US11619964B2

公开(公告)日：2023-04-04

申请号：US17385412

申请日：2021-07-26

申请人： Micron Technology, Inc.

发明人： Hyunui Lee ,  Won Joo Yun

IPC分类号： G06F1/12 ,  G06F1/10 ,  G06F1/08

摘要： Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.

公开(公告)号：US20240249766A1

公开(公告)日：2024-07-25

申请号：US18506208

申请日：2023-11-10

申请人： Micron Technology, Inc.

发明人： Jinha Hwang ,  Won Joo Yun

IPC分类号： G11C11/4091 ,  G11C11/4076 ,  G11C11/4093

CPC分类号： G11C11/4091 ,  G11C11/4076 ,  G11C11/4093

摘要： A semiconductor device includes an interface configured to receive clock signals and data signals. The interface includes a dual-tail latch. The dual-tail latch includes a sensing stage configured to sense and to amplify a differential voltage between at least a portion of the data signals and another signal. The sensing stage includes a first node and a second node between which the amplified differential voltage is output from the sensing stage. The dual-tail latch also includes a latch stage configured to latch a first latched value and a second latched value based at least in part on the amplified differential voltage. Moreover, the differential voltage is based at least in part on a previous first value and a previous second value from the latch stage fed back to the sensing stage.

公开(公告)号：US11996162B2

公开(公告)日：2024-05-28

申请号：US17831251

申请日：2022-06-02

申请人： Micron Technology, Inc.

发明人： William C. Waldrop ,  Won Joo Yun

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  H03K19/20

CPC分类号： G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  H03K19/20

摘要： Systems and methods that may enable alignment of a receiver enable signal with one or more clocking signals. By aligning the receiver operations with the one or more clocking signals, a likelihood of a false or incorrect data capture may be reduced, which may improve operation of a memory system. Reducing a likelihood of incorrect data capture may increase an accuracy of a distortion correction operation of a decision feedback equalizer (DFE).

公开(公告)号：US11886376B2

公开(公告)日：2024-01-30

申请号：US17398863

申请日：2021-08-10

申请人： Micron Technology, Inc.

发明人： Won Joo Yun ,  Sang-Hoon Shin

IPC分类号： G06F15/78 ,  G11C7/10 ,  G11C5/02 ,  G11C5/14 ,  G11C29/02

CPC分类号： G06F15/7871 ,  G06F15/7892 ,  G11C7/1057 ,  G11C7/1084

摘要： An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. An reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

公开(公告)号：US20230395105A1

公开(公告)日：2023-12-07

申请号：US17831251

申请日：2022-06-02

申请人： Micron Technology, Inc.

发明人： William C. Waldrop ,  Won Joo Yun

IPC分类号： G11C7/10 ,  G11C7/22 ,  H03K19/20

CPC分类号： G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  H03K19/20

摘要： Systems and methods that may enable alignment of a receiver enable signal with one or more clocking signals. By aligning the receiver operations with the one or more clocking signals, a likelihood of a false or incorrect data capture may be reduced, which may improve operation of a memory system. Reducing a likelihood of incorrect data capture may increase an accuracy of a distortion correction operation of a decision feedback equalizer (DFE).

公开(公告)号：US11922996B2

公开(公告)日：2024-03-05

申请号：US17449861

申请日：2021-10-04

申请人： MICRON TECHNOLOGY, INC.

发明人： Hyunui Lee ,  Won Joo Yun

IPC分类号： G11C11/4093 ,  G11C11/4076 ,  H01L25/18

CPC分类号： G11C11/4093 ,  G11C11/4076 ,  H01L25/18

摘要： A semiconductor device may include one or more output drivers. An output driver may be adjusted for impedance matching by applying a body voltage to one or more transistors of the output driver. In some examples, the body voltage applied may be based on a comparison between a reference voltage and a voltage at an external terminal. In some examples, the semiconductor device may include a calibration circuit that includes a comparator and an up/down counter that, based on a signal from the comparator, generates a code indicating the body voltage to be applied. The body voltage may be applied by a voltage generator in some examples.

公开(公告)号：US20220303111A1

公开(公告)日：2022-09-22

申请号：US17204681

申请日：2021-03-17

申请人： Micron Technology, Inc.

发明人： Hyunui Lee ,  Won Joo Yun ,  Baekkyu Choi

IPC分类号： H04L7/02

摘要： The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.

公开(公告)号：US20220164269A1

公开(公告)日：2022-05-26

申请号：US16953828

申请日：2020-11-20

申请人： Micron Technology, Inc.

发明人： Sang-Hoon Shin ,  Won Joo Yun ,  Rajesh H. Kariya

IPC分类号： G06F11/27 ,  G06F13/20 ,  G06F1/12

摘要： Test input/output speed conversion and related apparatuses and methods are disclosed. An apparatus includes a glue circuit and a BIST circuit for core circuitry of an integrated circuit device. The, the BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glue circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glue circuit is configured to convert between second speed test interface signals and second speed input/output signals operating at a second speed and first speed test interface signals and first speed input/output signals operating at the first speed. The second speed is different from the first speed.