公开(公告)号：US11688460B2

公开(公告)日：2023-06-27

申请号：US17491070

申请日：2021-09-30

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Nevil N. Gajera ,  John Frederic Schreck

IPC: G11C13/00

CPC classification number: G11C13/0026 ,  G11C13/003 ,  G11C13/0004 ,  G11C13/0028

Abstract: As described, an apparatus may include a memory cell corresponding to a memory address and an access line forming at least a portion of the memory cell. The apparatus may include a first decoder associated with a first delivery driver coupled to a first end of the access line and a second decoder associated with a second delivery driver coupled to another end of the access line.

公开(公告)号：US20220020430A1

公开(公告)日：2022-01-20

申请号：US17491070

申请日：2021-09-30

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Nevil N. Gajera ,  John Frederic Schreck

IPC: G11C13/00

Abstract: As described, an apparatus may include a memory cell corresponding to a memory address and an access line forming at least a portion of the memory cell. The apparatus may include a first decoder associated with a first delivery driver coupled to a first end of the access line and a second decoder associated with a second delivery driver coupled to another end of the access line.

公开(公告)号：US11139023B1

公开(公告)日：2021-10-05

申请号：US16824104

申请日：2020-03-19

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Nevil N. Gajera ,  John Frederic Schreck

IPC: G11C13/00

Abstract: As described, an apparatus may include a memory cell corresponding to a memory address and an access line forming at least a portion of the memory cell. The apparatus may include a first decoder associated with a first delivery driver coupled to a first end of the access line and a second decoder associated with a second delivery driver coupled to another end of the access line.

公开(公告)号：US20210295910A1

公开(公告)日：2021-09-23

申请号：US16824104

申请日：2020-03-19

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Nevil N. Gajera ,  John Frederic Schreck

IPC: G11C13/00

Abstract: As described, an apparatus may include a memory cell corresponding to a memory address and an access line forming at least a portion of the memory cell. The apparatus may include a first decoder associated with a first delivery driver coupled to a first end of the access line and a second decoder associated with a second delivery driver coupled to another end of the access line.