公开(公告)号：US11670358B2

公开(公告)日：2023-06-06

申请号：US17496728

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock ,  Evan C. Pearson

IPC: G11C7/00 ,  G11C11/4076 ,  H01L25/065

CPC classification number: G11C11/4076 ,  H01L25/0657 ,  H01L2225/06541

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

公开(公告)号：US20220028443A1

公开(公告)日：2022-01-27

申请号：US17496728

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock ,  Evan C. Pearson

IPC: G11C11/4076 ,  H01L25/065

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

公开(公告)号：US20230037145A1

公开(公告)日：2023-02-02

申请号：US17962188

申请日：2022-10-07

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Michael Kaminski ,  Joshua E. Alzheimer ,  John H. Gentry

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4074

Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

公开(公告)号：US20210174859A1

公开(公告)日：2021-06-10

申请号：US16706548

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock ,  Evan C. Pearson

IPC: G11C11/4076 ,  H01L25/065

Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.

公开(公告)号：US20210241821A1

公开(公告)日：2021-08-05

申请号：US17234725

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Michael Kaminski ,  Joshua E. Alzheimer ,  John H. Gentry

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4074

Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

公开(公告)号：US20210173773A1

公开(公告)日：2021-06-10

申请号：US16706635

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： Evan C. Pearson ,  John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock

IPC: G06F12/06 ,  G06F11/07 ,  H01L25/065 ,  G11C11/407

Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

公开(公告)号：US10991413B2

公开(公告)日：2021-04-27

申请号：US16502680

申请日：2019-07-03

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Michael Kaminski ,  Joshua E. Alzheimer ,  John H. Gentry

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4096

Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

公开(公告)号：US20240126692A1

公开(公告)日：2024-04-18

申请号：US18396638

申请日：2023-12-26

Applicant: Micron Technology, Inc.

Inventor： Evan C. Pearson ,  John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock

IPC: G06F12/06 ,  G06F11/07 ,  G11C11/407 ,  G11C29/04 ,  H01L25/065

CPC classification number: G06F12/0646 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0793 ,  G11C11/407 ,  G11C29/04 ,  H01L25/0657 ,  H01L2225/06541

Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

公开(公告)号：US11868252B2

公开(公告)日：2024-01-09

申请号：US16706635

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： Evan C. Pearson ,  John H. Gentry ,  Michael J. Scott ,  Greg S. Gatlin ,  Lael H. Matthews ,  Anthony M. Geidl ,  Michael Roth ,  Markus H. Geiger ,  Dale H. Hiscock

IPC: G06F11/07 ,  G06F12/06 ,  H01L25/065 ,  G11C11/407 ,  G11C29/04

CPC classification number: G06F12/0646 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0793 ,  G11C11/407 ,  G11C29/04 ,  H01L25/0657 ,  H01L2225/06541

Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

公开(公告)号：US11250890B2

公开(公告)日：2022-02-15

申请号：US17183202

申请日：2021-02-23

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Michael Kaminski ,  Joshua E. Alzheimer ,  John H. Gentry

IPC: G11C5/14 ,  G11C7/22 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4074

Abstract: Memory devices and systems with configurable die powerup delay, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die has a powerup group terminal and powerup group detect circuitry. The powerup group detect circuitry is configured to detect a powerup group assigned to the at least one memory die. The at least one memory die is configured to delay its powerup operation by a time delay corresponding to the powerup group to which it is assigned. In this manner, powerup operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.