公开(公告)号：US20210295901A1

公开(公告)日：2021-09-23

申请号：US17338191

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/406 ,  G11C29/00 ,  G11C11/409 ,  G11C11/4074

Abstract: Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.

公开(公告)号：US11024367B2

公开(公告)日：2021-06-01

申请号：US17017545

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C5/02 ,  G11C11/4093 ,  G11C11/406 ,  G11C7/18 ,  H01L25/10 ,  G11C11/4096

Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.

公开(公告)号：US11276454B2

公开(公告)日：2022-03-15

申请号：US16939669

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C16/34 ,  G11C11/406 ,  G11C11/4074 ,  G11C16/10 ,  G11C11/4072

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

公开(公告)号：US20210241821A1

公开(公告)日：2021-08-05

申请号：US17234725

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Michael Kaminski ,  Joshua E. Alzheimer ,  John H. Gentry

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4074

Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

公开(公告)号：US10991413B2

公开(公告)日：2021-04-27

申请号：US16502680

申请日：2019-07-03

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Michael Kaminski ,  Joshua E. Alzheimer ,  John H. Gentry

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4096

Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

公开(公告)号：US20200211626A1

公开(公告)日：2020-07-02

申请号：US16237115

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/4093 ,  G11C11/406 ,  G11C11/4096 ,  G11C5/02 ,  H01L25/10 ,  G11C7/18

Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.

公开(公告)号：US20230037145A1

公开(公告)日：2023-02-02

申请号：US17962188

申请日：2022-10-07

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Michael Kaminski ,  Joshua E. Alzheimer ,  John H. Gentry

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4074

Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

公开(公告)号：US20220189540A1

公开(公告)日：2022-06-16

申请号：US17684235

申请日：2022-03-01

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/406 ,  G11C11/4074 ,  G11C16/10 ,  G11C11/4072

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

公开(公告)号：US10762946B2

公开(公告)日：2020-09-01

申请号：US16237013

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/406 ,  G11C11/4074 ,  G11C16/10 ,  G11C11/4072

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a plurality of memory cells arranged in a plurality of memory regions and (ii) inhibit circuitry. In some embodiments, the inhibit circuitry is configured to disable one or more memory regions of the plurality of memory regions from receiving refresh commands such that memory cells of the one or more memory regions are not refreshed during refresh operations of the memory device. In these and other embodiments, the memory controller is configured to track memory regions that include utilized memory cells and/or to write data to the memory regions in accordance with a programming sequence of the memory device.

公开(公告)号：US11581031B2

公开(公告)日：2023-02-14

申请号：US17338191

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C16/04 ,  G11C11/406 ,  G11C29/00 ,  G11C11/409 ,  G11C11/4074

Abstract: Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.