公开(公告)号：US20240339149A1

公开(公告)日：2024-10-10

申请号：US18749412

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C11/408 ,  G11C11/4091 ,  G11C13/00

CPC classification number: G11C11/4087 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2211/4013

Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.

公开(公告)号：US11605418B2

公开(公告)日：2023-03-14

申请号：US17080310

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C13/00 ,  G11C11/408 ,  G11C11/4091

Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.

公开(公告)号：US12020743B2

公开(公告)日：2024-06-25

申请号：US18182305

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C13/00 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/4087 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2211/4013

Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.

公开(公告)号：US20230215489A1

公开(公告)日：2023-07-06

申请号：US18182305

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C11/408 ,  G11C11/4091 ,  G11C13/00

CPC classification number: G11C11/4087 ,  G11C11/4091 ,  G11C13/004 ,  G11C13/0026 ,  G11C13/0002 ,  G11C13/0069 ,  G11C13/003 ,  G11C13/0023 ,  G11C2013/0045 ,  G11C2211/4013

Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.

公开(公告)号：US20220130447A1

公开(公告)日：2022-04-28

申请号：US17080310

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4094

Abstract: Embodiments relate to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. Embodiments are directed to writing and reading memory cell pairs.