公开(公告)号：US20250013391A1

公开(公告)日：2025-01-09

申请号：US18773306

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Jameer Mulani ,  Jotiba Koparde

IPC: G06F3/06

Abstract: Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.

公开(公告)号：US20250094071A1

公开(公告)日：2025-03-20

申请号：US18900333

申请日：2024-09-27

Applicant: Micron Technology, Inc.

Inventor： Jotiba Koparde

IPC: G06F3/06

Abstract: Methods, systems, and devices for techniques for data transfer operations are described. A memory system may select a source set of memory cells and a destination set of memory cells using one or more counters corresponding to access operations for the source and the destination. For example, as part of a data transfer operation, the memory system may prioritize transferring data from a block with a lower quantity of read operations to a block with a lower quantity of access operations. In some cases, the memory system may prioritize transferring data from a page with a lower quantity of read operations to a page with a slower read duration.

公开(公告)号：US20230176778A1

公开(公告)日：2023-06-08

申请号：US17457829

申请日：2021-12-06

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Jameer Mulani ,  Jotiba Koparde

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0667 ,  G06F3/0673

Abstract: Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.

公开(公告)号：US12124723B2

公开(公告)日：2024-10-22

申请号：US17729837

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Jotiba Koparde

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673

Abstract: Methods, systems, and devices for techniques for data transfer operations are described. A memory system may select a source set of memory cells and a destination set of memory cells using one or more counters corresponding to access operations for the source and the destination. For example, as part of a data transfer operation, the memory system may prioritize transferring data from a block with a lower quantity of read operations to a block with a lower quantity of access operations. In some cases, the memory system may prioritize transferring data from a page with a lower quantity of read operations to a page with a slower read duration.

公开(公告)号：US20240281346A1

公开(公告)日：2024-08-22

申请号：US18434461

申请日：2024-02-06

Applicant: Micron Technology, Inc.

Inventor： Jotiba Koparde ,  Nicola Colella ,  Sridhar Prudviraj Gunda

IPC: G06F11/16 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/1658 ,  G06F11/0787 ,  G06F11/1016

Abstract: Methods, systems, and devices for programming failure handling during data folding are described. A memory system may support a non-blocking exception handling process for handling program failures that occur during folding. For example, if a program failure occurs at a given page, the memory system may mark the failed page as storing uncorrectable data (e.g., associated with an uncorrectable error correction code (UECC) error) rather than as being associated with the program failure. Based on the marking, the memory system may continue the folding operation, allowing the data to be moved to another page of a physical destination block. After the folding operation is complete, the memory system may replace a failed physical destination block that includes the failed page with a spare block and retire the failed physical destination block.

公开(公告)号：US12061819B2

公开(公告)日：2024-08-13

申请号：US17457829

申请日：2021-12-06

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Jameer Mulani ,  Jotiba Koparde

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0667 ,  G06F3/0673

Abstract: Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.

公开(公告)号：US20230342060A1

公开(公告)日：2023-10-26

申请号：US17729837

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Jotiba Koparde

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673

Abstract: Methods, systems, and devices for techniques for data transfer operations are described. A memory system may select a source set of memory cells and a destination set of memory cells using one or more counters corresponding to access operations for the source and the destination. For example, as part of a data transfer operation, the memory system may prioritize transferring data from a block with a lower quantity of read operations to a block with a lower quantity of access operations. In some cases, the memory system may prioritize transferring data from a page with a lower quantity of read operations to a page with a slower read duration.