公开(公告)号：US20250117344A1

公开(公告)日：2025-04-10

申请号：US18789677

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Keun-Soo Song

IPC: G06F13/16

Abstract: Disclosed are methods, systems, and apparatuses for semiconductor memory devices (e.g., dynamic random access memory (DRAM)) that include a command/address inversion (CAI) input signal indicating whether command/address inputs to the memory devices are inverted. The CAI input signal may be generated by a memory controller, a registering clock driver (RCD), or other component coupled to the memory devices, and the component may generate the CAI input signal differently for the different memory devices to which the component is coupled. As described herein, the component may dynamically generate the CAI input signal based on the values of the command/address inputs so as to reduce power consumption by the memory devices while retaining signal integrity.

公开(公告)号：US20250157528A1

公开(公告)日：2025-05-15

申请号：US18923616

申请日：2024-10-22

Applicant: Micron Technology, Inc.

Inventor： Keun-Soo Song ,  Mark K. Hadrick

IPC: G11C11/4096 ,  G11C11/4093

Abstract: Methods, apparatuses, and systems related to operations for executing mode register read and mode register write all commands. A memory device can execute a register read or a mode register write all command using a unit interval of one or more DQs. One or more command address pins can be designated to store groups of mode registers. The memory device can read or write mode register information associated with the group of mode registers through a pre-defined number of DQs, burst length, and die configuration.

公开(公告)号：US20250157527A1

公开(公告)日：2025-05-15

申请号：US18923597

申请日：2024-10-22

Applicant: Micron Technology, Inc.

Inventor： Keun-Soo Song ,  Mark K. Hadrick

IPC: G11C11/4096 ,  G11C11/4093

Abstract: Methods, apparatuses, and systems related to operations for executing mode register read and mode register write all commands. A memory device can execute a register read or a mode register write all command using a unit interval of one or more DQs. One or more command address pins can be designated to store groups of mode registers. The memory device can read or write mode register information associated with the group of mode registers through a pre-defined number of DQs, burst length, and die configuration.