公开(公告)号：US20240347096A1

公开(公告)日：2024-10-17

申请号：US18628127

申请日：2024-04-05

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Mark Kalei Hadrick ,  HyunYoo Lee ,  KeunSoo Song ,  John Christopher Sancon ,  Kang-Yong Kim

IPC: G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/40611 ,  G11C11/4096

Abstract: Apparatuses and techniques for implementing usage-based disturbance counter clearance are described. In example implementations, a memory device includes a memory array having multiple rows. The memory device also includes multiple usage-based disturbance counters that are associated with the memory array. The memory device further includes logic that performs a refresh operation on a row of the multiple rows responsive to a refresh command. The logic also clears a usage-based disturbance counter of the multiple usage-based disturbance counters responsive to the refresh command. Here, the usage-based disturbance counter stores a quantity of accesses to the row of the multiple rows. This can reduce a frequency of performing usage-based disturbance mitigation procedures that would otherwise be applied to the multiple usage-based disturbance counters, thereby saving power and avoiding denial-of-service periods with the memory array.