公开(公告)号：US12154879B2

公开(公告)日：2024-11-26

申请号：US18231185

申请日：2023-08-07

Applicant: Micron Technology, Inc.

Inventor： Ko Han Lin ,  Tsung Che Tsai

IPC: H01L23/00

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

公开(公告)号：US20230402418A1

公开(公告)日：2023-12-14

申请号：US18231185

申请日：2023-08-07

Applicant: Micron Technology, Inc.

Inventor： Ko Han Lin ,  Tsung Che Tsai

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/11 ,  H01L24/06 ,  H01L24/03 ,  H01L2224/06102 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/0362 ,  H01L2224/1403

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

公开(公告)号：US20250087614A1

公开(公告)日：2025-03-13

申请号：US18957594

申请日：2024-11-22

Applicant: Micron Technology, Inc.

Inventor： Ko Han Lin ,  Tsung Che Tsai

IPC: H01L23/00

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

公开(公告)号：US11742309B2

公开(公告)日：2023-08-29

申请号：US17000176

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Ko Han Lin ,  Tsung Che Tsai

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L2224/0362 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/1403

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

公开(公告)号：US20220059485A1

公开(公告)日：2022-02-24

申请号：US17000176

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Ko Han Lin ,  Tsung Che Tsai

IPC: H01L23/00

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.