公开(公告)号：US12154879B2

公开(公告)日：2024-11-26

申请号：US18231185

申请日：2023-08-07

Applicant: Micron Technology, Inc.

Inventor： Ko Han Lin ,  Tsung Che Tsai

IPC: H01L23/00

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

公开(公告)号：US20250087614A1

公开(公告)日：2025-03-13

申请号：US18957594

申请日：2024-11-22

Applicant: Micron Technology, Inc.

Inventor： Ko Han Lin ,  Tsung Che Tsai

IPC: H01L23/00

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

公开(公告)号：US20220059485A1

公开(公告)日：2022-02-24

申请号：US17000176

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Ko Han Lin ,  Tsung Che Tsai

IPC: H01L23/00

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

公开(公告)号：US20240371824A1

公开(公告)日：2024-11-07

申请号：US18605161

申请日：2024-03-14

Applicant: Micron Technology, Inc.

Inventor： Yichen Wang ,  Tsung Che Tsai ,  Vibhav Gupta ,  Wei Chang Wong ,  Raj K. Bansal

IPC: H01L23/00 ,  H01L21/3065 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/544 ,  H10B80/00

Abstract: A semiconductor device including a semiconductor die and an encapsulant material disposed at the edges of the semiconductor die and among the plurality of fin shape structures. The semiconductor die further includes a substrate, a functional die region disposed in a center of the semiconductor die, the functional die region having a stack layer structure within which a plurality of dielectric layers and a plurality of electrically conductive layers alternatively stacked, and a die edge region disposed at edges of the semiconductor die, the die edge region including a plurality of fin shape structures protruding along a horizontal direction to a sidewall of the semiconductor device.

公开(公告)号：US20230402418A1

公开(公告)日：2023-12-14

申请号：US18231185

申请日：2023-08-07

Applicant: Micron Technology, Inc.

Inventor： Ko Han Lin ,  Tsung Che Tsai

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/11 ,  H01L24/06 ,  H01L24/03 ,  H01L2224/06102 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/0362 ,  H01L2224/1403

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

公开(公告)号：US11810822B2

公开(公告)日：2023-11-07

申请号：US17481489

申请日：2021-09-22

Applicant: Micron Technology, Inc.

Inventor： Shigeru Sugioka ,  Keizo Kawakita ,  Raj K. Bansal ,  Tsung Che Tsai

IPC: H01L21/00 ,  H01L21/784 ,  H01L23/544

CPC classification number: H01L21/784 ,  H01L23/544 ,  H01L2223/5446

Abstract: Apparatuses including structures in scribe lines are described. An example apparatus includes: a first chip and a second chip; a scribe region between the first chip and the second chip; a crack guide region in the scribe region, the crack guide region including a dicing line along which the first chip and the second chip are to be divided; and a structure disposed in the crack guide region and extending along the dicing line.

公开(公告)号：US11742309B2

公开(公告)日：2023-08-29

申请号：US17000176

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Ko Han Lin ,  Tsung Che Tsai

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L2224/0362 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/1403

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.