公开(公告)号：US20240355766A1

公开(公告)日：2024-10-24

申请号：US18448407

申请日：2023-08-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Pin Chiu ,  Yu-Bey Wu ,  Dian-Hau Chen

IPC分类号： H01L23/00 ,  H01L23/485

CPC分类号： H01L24/06 ,  H01L23/485 ,  H01L24/03 ,  H01L2224/03005 ,  H01L2224/06102

摘要： A first bond pad of a first device and a second bond pad of a second device are implanted with metal ions. The first and second semiconductor device are bonded together using a direct metal-to-metal bond and an overlay offset occurs between the bond pads such that a portion of the first bond pad and a portion of the second bond pad overlaps and contacts a dielectric material layer. During the bonding process, however, diffusion of the metal ions provides a barrier layer at the interface of the bond pads and the dielectric layers.

公开(公告)号：US20240096760A1

公开(公告)日：2024-03-21

申请号：US18522271

申请日：2023-11-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC分类号： H01L23/49503 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/06 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/96 ,  H01L24/97 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/05 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/023 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2224/09051 ,  H01L2224/09055 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/18 ,  H01L2224/225 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/82986 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2924/18162 ,  H01L2924/37001

摘要： A semiconductor package includes a chip, a redistribution structure, and first under- ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.

公开(公告)号：US20240071942A1

公开(公告)日：2024-02-29

申请号：US18120826

申请日：2023-03-13

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Young kun JEE ,  Jihwan HWANG ,  Chungsun LEE

IPC分类号： H01L23/538 ,  H01L23/00

CPC分类号： H01L23/5386 ,  H01L23/5384 ,  H01L24/06 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/08146

摘要： A semiconductor chip including a semiconductor substrate having first and second surfaces, a transistor on the first surface, a first interlayer dielectric layer on the transistor, a second interlayer dielectric layer on the first interlayer dielectric layer, a wiring line in the second interlayer dielectric layer, a first conductive pad on the second interlayer dielectric layer, a first passivation layer on the second interlayer dielectric layer, a second conductive pad in the first passivation layer, a through via penetrating the semiconductor substrate and the first interlayer dielectric layer to come into connection with the wiring line, a second passivation layer on the second surface, and a third conductive pad in the second passivation layer and connected to the through via. The first passivation layer has a first thickness 0.4 to 0.6 times a second thickness between the first surface and a top surface of the second passivation layer.

公开(公告)号：US11791303B2

公开(公告)日：2023-10-17

申请号：US18099092

申请日：2023-01-19

申请人： Samsung Electronics Co., Ltd.

发明人： Hyungu Kang ,  Jaekyu Sung

IPC分类号： H01L23/00 ,  H01L25/18 ,  H01L23/498

CPC分类号： H01L24/73 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L25/18 ,  H01L2224/06102 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48148 ,  H01L2224/48158 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/182

摘要： A semiconductor package may include a semiconductor chip on a package substrate. The semiconductor package may include a plurality of conductive connections connecting the semiconductor chip to the package substrate may be disposed, a plurality of towers which are apart from one another and each include a plurality of memory chips may be disposed, wherein a lowermost memory chip of each of the plurality of towers overlaps the semiconductor chip from a top-down view. The semiconductor package further includes a plurality of adhesive layers be attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip.

公开(公告)号：US20230207490A1

公开(公告)日：2023-06-29

申请号：US17976625

申请日：2022-10-28

申请人： Micron Technology, Inc.

发明人： Yung Sheng Zou ,  Yun Ting Hsu

IPC分类号： H01L23/58 ,  H01L23/00

CPC分类号： H01L23/58 ,  H01L24/08 ,  H01L24/05 ,  H01L24/06 ,  H01L24/49 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/08113 ,  H01L2224/48091 ,  H01L2224/48229 ,  H01L2224/49107

摘要： A semiconductor device assembly including a substrate, a surface-mount device (SMD) electrical component attached to the substrate is provided. The SMD electrical component includes a first contact and a second contact, and at least a first wire bond electrically and physically coupled directly to the first contact.

公开(公告)号：US20230163089A1

公开(公告)日：2023-05-25

申请号：US17934298

申请日：2022-09-22

申请人： Samsung Electronics Co., Ltd.

发明人： Minki Kim ,  Seungduk Baek

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC分类号： H01L24/08 ,  H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L25/0652 ,  H01L23/481 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/05017 ,  H01L2224/05557 ,  H01L2224/08225 ,  H01L2225/06527 ,  H01L2225/06544

摘要： A semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface thereof. The first semiconductor chip may include a first bonding pad on a top surface of a first semiconductor substrate and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second interconnection pattern on a bottom surface of a second semiconductor substrate and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than that of the first bonding pad, and a width of the second interconnection pattern may be larger than that of the second bonding pad.

公开(公告)号：US20180040577A1

公开(公告)日：2018-02-08

申请号：US15667610

申请日：2017-08-02

申请人： Dyi-Chung HU

发明人： Dyi-Chung HU

IPC分类号： H01L23/00

CPC分类号： H01L24/06 ,  H01L23/498 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

摘要： A pad structure adapted to be disposed on a first package substrate and electrically connected to conductive contacts of a second package substrate includes a first conductive pad having a first top surface, a second conductive pad, a first leveling conductor and a second leveling conductor is provided. The second conductive pad disposed aside the first conductive pad has a second top surface non-coplanar with the first top surface. The first leveling conductor disposed on the first conductive pad has a first leveling surface opposite to the first top surface. The second leveling conductor disposed on the second conductive pad and having a second leveling surface opposite to the second top surface is coplanar with the first leveling surface. The conductive contacts of the second package substrate are disposed on the first leveling conductor and the second leveling conductor. A manufacturing method of a pad structure is also provided.

公开(公告)号：US09859196B2

公开(公告)日：2018-01-02

申请号：US15251127

申请日：2016-08-30

申请人： STMicroelectronics (Shenzhen) R&D Co. Ltd.

发明人： Jing-En Luan

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/48 ,  H01L23/433 ,  H01L23/367 ,  H01L23/498 ,  H01L21/768 ,  H01L23/482 ,  H01L23/28 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L23/49531 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76885 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/482 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/16 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/03003 ,  H01L2224/03334 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06177 ,  H01L2224/09151 ,  H01L2224/12105 ,  H01L2224/16238 ,  H01L2224/32221 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/85 ,  H01L2224/92127 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2224/81 ,  H01L2924/00012

摘要： An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads extend to a bottom surface of the encapsulation material defining first contact pads. The electronic device may include bond wires between the first bond pads and corresponding ones of the leads, and conductors extending from corresponding ones of the second bond pads to the bottom surface of the encapsulation material defining second contact pads.

公开(公告)号：US09818815B2

公开(公告)日：2017-11-14

申请号：US14961622

申请日：2015-12-07

申请人： Renesas Electronics Corporation

发明人： Takuo Funaya ,  Hiromi Shigihara ,  Hisao Shigihara

IPC分类号： H01L49/02 ,  H01L23/495 ,  H01L23/522 ,  H01L27/06 ,  H01L27/12 ,  H01L23/00

CPC分类号： H01L28/10 ,  H01L23/49575 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0617 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06102 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4945 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a main surface; a first coil formed on the main surface; a first insulating film formed over the first coil and having a first main surface; a second insulating film formed on the first main surface of the first insulating film and having a second main surface; and a second coil formed on the second main surface of the second insulating film, wherein the first main surface of the first insulating film has a first area on which the second insulating film is formed, and has a second area without the first area in a plan view, and wherein the second insulating film is surrounded with the second area in the plane view.

公开(公告)号：US20170309588A1

公开(公告)日：2017-10-26

申请号：US15646721

申请日：2017-07-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chita Chuang ,  Chen-Shien Chen

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/56 ,  H01L23/58 ,  H01L23/31 ,  H01L21/60

CPC分类号： H01L24/17 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/522 ,  H01L23/53238 ,  H01L23/562 ,  H01L23/585 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2021/60255 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06102 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/14152 ,  H01L2224/14179 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/206 ,  H01L2924/00

摘要： A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.