公开(公告)号：US20020179990A1

公开(公告)日：2002-12-05

申请号：US10200413

申请日：2002-07-22

Applicant: Micron Technology, Inc.

Inventor： Mark Fischer ,  Zhiping Yin ,  Thomas R. Glass ,  Kunal R. Parekh ,  Gurtej Singh Sandhu

IPC: H01L021/82

CPC classification number: H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.

公开(公告)号：US20030030093A1

公开(公告)日：2003-02-13

申请号：US10223805

申请日：2002-08-19

Applicant: Micron Technology, Inc.

Inventor： Vishnu K. Agarwal ,  F. Daniel Gealy ,  Kunal R. Parekh ,  Randhir P.S. Thakur

IPC: H01L021/8242 ,  H01L027/108 ,  H01L029/94 ,  H01L031/119

CPC classification number: H01L28/40 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5222 ,  H01L28/57 ,  H01L28/84 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor forming method can include forming an insulation layer over a substrate and forming a barrier layer to threshold voltage shift inducing material over the substrate. An opening can be formed at least into the insulation layer and a capacitor dielectric layer formed at least within the opening. Threshold voltage inducing material can be provided over the barrier layer but be retarded in movement into an electronic device comprised by the substrate. The dielectric layer can comprise a tantalum oxide and the barrier layer can include a silicon nitride. Providing threshold voltage shift inducing material can include oxide annealing dielectric layer such as with N2O. The barrier layer can be formed over the insulation layer, the insulation layer can be formed over the barrier layer, or the barrier layer can be formed over a first insulation layer with a second insulation layer formed over the barrier layer. Further, the barrier layer can be formed after forming the capacitor electrode or after forming the dielectric layer, for example, by using poor step coverage deposition methods.

公开(公告)号：US20040241957A1

公开(公告)日：2004-12-02

申请号：US10799794

申请日：2004-03-11

Applicant: Micron Technology, Inc.

Inventor： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

IPC: H01L021/76

CPC classification number: H01L21/76232 ,  H01L21/0332 ,  H01L21/76235

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride laver and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

Abstract translation: 一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物紫菜和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。 另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。