公开(公告)号：US09702305B2

公开(公告)日：2017-07-11

申请号：US13864413

申请日：2013-04-17

Applicant: Micron Technology, Inc.

Inventor： William H. Radke ,  Laszlo Borbely ,  David Christopher Pruett

IPC: G06F9/00 ,  G06F9/44 ,  F02D25/00 ,  G06F13/16

CPC classification number: F02D25/00 ,  G06F13/1668

Abstract: Multiple engine sequencers in memory interfaces are disclosed. Individual sequencer engines of multiple engine sequencers perform at least portions of their respective operations in parallel with other individual sequencer engine operations performed in the memory interface. In at least one embodiment, sequencer engine operations are performed at least partially concurrently with other sequencer engine operations in the memory interface.

公开(公告)号：US20140316684A1

公开(公告)日：2014-10-23

申请号：US13864413

申请日：2013-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke ,  Laszlo Borbely ,  David Christopher Pruett

IPC: F02D25/00

CPC classification number: F02D25/00 ,  G06F13/1668

Abstract: Multiple engine sequencers in memory interfaces are disclosed. Individual sequencer engines of multiple engine sequencers perform at least portions of their respective operations in parallel with other individual sequencer engine operations performed in the memory interface. In at least one embodiment, sequencer engine operations are performed at least partially concurrently with other sequencer engine operations in the memory interface.

Abstract translation: 公开了存储器接口中的多个引擎排序器。 多个引擎定序器的单独定序引擎与其在存储器接口中执行的其他单独的定序器引擎操作并行执行其相应操作的至少一部分。 在至少一个实施例中，定序器引擎操作至少部分地与存储器接口中的其他定序器引擎操作同时执行。