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公开(公告)号：US11494084B2
公开(公告)日：2022-11-08
申请号：US17119576
申请日：2020-12-11
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Miranda
Abstract: Control logic in a memory device identifies a request to execute a memory access operation on the memory cell. A first set of pulses corresponding to a first voltage ramp slope level is caused to be applied to the memory cell during a first time interval of the memory access operation. The control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first slope level and the second slope level are different.
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公开(公告)号：US20220187995A1
公开(公告)日：2022-06-16
申请号：US17119576
申请日：2020-12-11
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Miranda
Abstract: Control logic in a memory device identifies a request to execute a memory access operation on the memory cell. A first set of pulses corresponding to a first voltage ramp slope level is caused to be applied to the memory cell during a first time interval of the memory access operation. The control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first slope level and the second slope level are different.
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公开(公告)号：US12141445B2
公开(公告)日：2024-11-12
申请号：US17960304
申请日：2022-10-05
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Miranda
Abstract: Control logic in a memory device causes a first set of pulses corresponding to a first voltage ramp slope level to be applied to a memory cell during a first time interval of an execution of a memory access operation. In response to determining a transition time has been reached, the control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first voltage ramp slope level and the second voltage ramp slope level are different.
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公开(公告)号：US20230026558A1
公开(公告)日：2023-01-26
申请号：US17960304
申请日：2022-10-05
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Miranda
Abstract: Control logic in a memory device causes a first set of pulses corresponding to a first voltage ramp slope level to be applied to a memory cell during a first time interval of an execution of a memory access operation. In response to determining a transition time has been reached, the control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first voltage ramp slope level and the second voltage ramp slope level are different.
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