PROGRAM PULSE MODIFICATION
    2.
    发明公开

    公开(公告)号:US20240248612A1

    公开(公告)日:2024-07-25

    申请号:US18406852

    申请日:2024-01-08

    CPC classification number: G06F3/0619 G06F3/0659 G06F3/0679

    Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to modify pulses used to program memory components. The controller receives a request to program data in an individual memory component of a set of memory components. The controller computes a plurality of memory reliability criteria associated with the individual memory component and compares the plurality of memory reliability criteria to one or more threshold values. The controller selects a program pulse used to program the data to the individual memory component based on a result of comparing the plurality of memory reliability criteria to the one or more threshold values.

    WORD LINE BASED PROGRAM VOLTAGE ADJUSTMENT

    公开(公告)号:US20240420784A1

    公开(公告)日:2024-12-19

    申请号:US18739769

    申请日:2024-06-11

    Abstract: Aspects of the present disclosure configure a memory sub-system controller to selectively adjust a program pulse for different word line groups of a memory sub-system. The controller receives a request to program data to an individual memory component of a set of memory components. The controller determines that a program erase count (PEC) associated with the individual memory component transgresses a threshold value. The controller, in response to determining that the PEC associated with the individual memory component transgresses the threshold value, selectively adjusts a predetermined program voltage (Vpgm) associated with a subset of word lines (WLs) of the individual memory component based on whether the subset of WLs is associated with an individual WL group (WLG). The controller programs the data to the individual memory component according to the selectively adjusted predetermined Vpgm.

    NAND DETECT PROGRAM COMPLETION (NDPC) WITH POWER OFF CHARGE LOSS CALIBRATION IN A MEMORY SUB-SYSTEM

    公开(公告)号:US20240371450A1

    公开(公告)日:2024-11-07

    申请号:US18637412

    申请日:2024-04-16

    Abstract: A system including a memory device and an operatively coupled processing device to perform operations including: responsive to detecting a power-up event, performing a first read strobe on a first set of a plurality of memory cells addressable by a first wordline, determining a value of a conductivity metric reflecting conductive states of one or more bitlines connected to the first set of the plurality of memory cells, determining, based on the value of the conductivity metric, a read level offset value for a second wordline, wherein the second wordline is adjacent to the first wordline, performing, using the read level offset value, a second read strobe on the second wordline, and responsive to determining that a value of a quality metric produced by the second read strobe satisfies a quality criterion, indicating that a programming operation performed on the second wordline was completed before a power off event.

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