公开(公告)号：US20160026565A1

公开(公告)日：2016-01-28

申请号：US14340976

申请日：2014-07-25

Applicant: Micron Technology, Inc.

Inventor： Tommaso Vali ,  Andrea Giovanni Xotta ,  Umberto Siciliani ,  Luca DeSantis ,  Michele Incarnati

IPC: G06F12/06 ,  G06F12/02

CPC classification number: G06F12/0646 ,  G06F12/023 ,  G06F12/0238 ,  G06F2212/1016 ,  G06F2212/251 ,  G06F2212/7208

Abstract: Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.

Abstract translation: 本文公开了同时访问不同存储器平面的装置和方法。 示例性设备可以包括与被配置为维护与多个存储器命令和地址对中的每一个相关联的相应信息的队列相关联的控制器。 控制器被配置为基于由队列维护的信息从多个存储器命令和地址对中选择一组存储器命令和地址对。 该示例设备还包括被配置为接收该组存储器命令和地址对的存储器。 存储器被配置为同时执行与该组存储器命令和地址对相关联的存储器访问操作。

公开(公告)号：US10402319B2

公开(公告)日：2019-09-03

申请号：US14340976

申请日：2014-07-25

Applicant: Micron Technology, Inc.

Inventor： Tommaso Vali ,  Andrea Giovanni Xotta ,  Umberto Siciliani ,  Luca DeSantis ,  Michele Incarnati

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/02

Abstract: Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.

公开(公告)号：US11550717B2

公开(公告)日：2023-01-10

申请号：US16548754

申请日：2019-08-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Andrea Giovanni Xotta ,  Umberto Siciliani ,  Luca DeSantis ,  Michele Incarnati

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/02

Abstract: Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.