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    Memory devices having differently configured blocks of memory cells
    2.
    发明授权
    Memory devices having differently configured blocks of memory cells 有权

    公开(公告)号：US10891188B2

    公开(公告)日：2021-01-12

    申请号：US16516611

    申请日：2019-07-19

    申请人： MICRON TECHNOLOGY, INC.

    发明人： William H. Radke ,  Tommaso Vali ,  Michele Incarnati

    IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G11C29/52

    摘要： A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of memory cells of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of memory cells of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block of memory cells.

    Apparatuses and methods for concurrently accessing different memory planes of a memory
    5.
    发明授权
    Apparatuses and methods for concurrently accessing different memory planes of a memory 有权

    公开(公告)号：US11955204B2

    公开(公告)日：2024-04-09

    申请号：US17959078

    申请日：2022-10-03

    申请人： Micron Technology, Inc.

    发明人： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

    IPC分类号： G06F3/06 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32

    CPC分类号： G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2209

    摘要： Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

    Pre-compensation of memory threshold voltage
    8.
    发明授权
    Pre-compensation of memory threshold voltage 有权
    内存阈值电压预补偿

    公开(公告)号：US09589659B1

    公开(公告)日：2017-03-07

    申请号：US15164171

    申请日：2016-05-25

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Tommaso Vali ,  Andrea D'Alessandro ,  Violante Moschiano ,  Mattia Cichocki ,  Michele Incarnati ,  Federica Paolini

    IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

    CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5621 ,  G11C2211/5648

    摘要： Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.

    摘要翻译： 操作存储器的方法包括将要编程的第一存储器单元的多个可能数据状态的第一目标数据状态存储在耦合到数据节点的目标数据锁存器中，存储多个第二目标数据状态的至少一位 要在与数据节点耦合的攻击者数据锁存器中编程的第二存储器单元的可能数据状态，以及编程第一存储器单元并对第一目标数据状态执行程序验证操作，以确定第一存储器单元是否被验证 第一个目标数据状态。 所述程序验证操作包括：基于存储在所述侵入者数据锁存器中的所述第二目标状态的所述至少一个位，执行所述中间验证时，对应于所述攻击量的中间验证以向所述数据节点施加电压; 以及基于存储在侵略者数据锁存器中的第二目标状态的至少一个位，在执行程序验证时，对应于不侵略条件的程序验证应用于数据节点的电压。 所述方法包括如果在中间验证期间验证第一存储器单元并且侵略者数据锁存器中的至少一个位对应于特定的侵略量，则禁止第一存储器单元进一步编程，或者在第一存储器单元期间验证第一存储器单元 程序验证，并且攻击者数据锁存中的至少一个位对应于无侵略的条件。 第二存储器单元是第一存储器单元的邻居。

    MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE
    9.
    发明申请
    MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE 有权
    用于存储器件的存储器件和配置方法

    公开(公告)号：US20150033096A1

    公开(公告)日：2015-01-29

    申请号：US14513880

    申请日：2014-10-14

    申请人： MICRON TECHNOLOGY, INC.

    发明人： William H. Radke ,  Tommaso Vali ,  Michele Incarnati

    IPC分类号： G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F11/10

    CPC分类号： G06F11/1048 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0629 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0207 ,  G06F12/0646 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/52

    摘要： A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells in a first configuration comprising one or more groups of overhead data memory cells, and to configure a second block of memory cells in a second configuration comprising one or more groups of user data memory cells and at least one group of overhead data memory cells. The first configuration is different than the second configuration. At least one group of overhead data memory cells of the second block of memory cells comprises a different storage capacity than at least one group of overhead data memory cells of the first block of memory cells.

    摘要翻译： 存储器设备具有多个可单独擦除的存储器单元块，以及控制器，被配置为配置包括一组或多组开销数据存储单元的第一配置中的第一存储单元块，并且配置存储器单元的第二块 包括一组或多组用户数据存储器单元和至少一组开销数据存储器单元的第二配置。 第一配置与第二配置不同。 存储器单元的第二块的至少一组开销数据存储单元包括与第一存储单元块的至少一组开销数据存储单元不同的存储容量。