公开(公告)号：US20190355803A1

公开(公告)日：2019-11-21

申请号：US16527301

申请日：2019-07-31

Applicant: Micron Technology, Inc.

Inventor： Muralikrishnan Balakrishnan ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L49/02 ,  H01L27/11507

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

公开(公告)号：US20240045604A1

公开(公告)日：2024-02-08

申请号：US17879581

申请日：2022-08-02

Applicant: Micron Technology, Inc.

Inventor： Zhuo Chen ,  Beth R. Cook ,  Dale W. Collins ,  Muralikrishnan Balakrishnan

IPC: G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for self-aligned techniques for forming connections in a memory device are described. A redistribution layer (RDL) for coupling an electrode of a capacitor of a memory cell with a corresponding selector device may be fabricated at a same time or stage as the electrode, using self-aligned techniques. When forming portions of a memory cell, a cavity for the electrode may be etched, and a portion of the RDL that extends from the electrode cavity to a corresponding selector device may also be selectively etched. The resulting cavities may be filled with an electrode material, which may form the electrode and couple the electrode to the corresponding selector device. The resulting memory device may support implementation of a staggered configuration for memory cells, and may include electrodes that share a crystalline structure with one or more corresponding portions of an RDL.

公开(公告)号：US20200279907A1

公开(公告)日：2020-09-03

申请号：US16874845

申请日：2020-05-15

Applicant: Micron Technology, Inc.

Inventor： Muralikrishnan Balakrishnan ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L49/02 ,  H01L27/11507

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

公开(公告)号：US10396145B2

公开(公告)日：2019-08-27

申请号：US15404576

申请日：2017-01-12

Applicant: Micron Technology, Inc.

Inventor： Muralikrishnan Balakrishnan ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/11507 ,  H01L49/02

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

公开(公告)号：US11600691B2

公开(公告)日：2023-03-07

申请号：US17125030

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Muralikrishnan Balakrishnan ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L49/02 ,  H01L27/11507

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

公开(公告)号：US10680057B2

公开(公告)日：2020-06-09

申请号：US16527301

申请日：2019-07-31

Applicant: Micron Technology, Inc.

Inventor： Muralikrishnan Balakrishnan ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/11507 ,  H01L49/02

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

公开(公告)号：US20210193663A1

公开(公告)日：2021-06-24

申请号：US16721006

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma ,  Muralikrishnan Balakrishnan

IPC: H01L27/108 ,  H01L27/11502 ,  H01L45/00 ,  H01L49/00 ,  H01L29/786 ,  G11C11/22

Abstract: Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

公开(公告)号：US20210104597A1

公开(公告)日：2021-04-08

申请号：US17125030

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Muralikrishnan Balakrishnan ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L49/02 ,  H01L27/11507

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

公开(公告)号：US20150333257A1

公开(公告)日：2015-11-19

申请号：US14806259

申请日：2015-07-22

Applicant: Micron Technology, Inc.

Inventor： D.V. Nirmal Ramaswamy ,  Sanh D. Tang ,  Alessandro Torsi ,  Muralikrishnan Balakrishnan ,  Xiaonan Chen ,  John K. Zahurak

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1641

Abstract: A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.

Abstract translation: 形成电阻式存储元件的方法包括在第一电极上形成氧化物材料。 将氧化物材料暴露于等离子体工艺以形成经处理的氧化物材料。 在经处理​​的氧化物材料上形成第二电极。 还描述了形成电阻性存储器元件以及相关的电阻性存储器元件，电阻存储器单元和电阻存储器件的附加方法。

公开(公告)号：US20210265355A1

公开(公告)日：2021-08-26

申请号：US17317693

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma ,  Muralikrishnan Balakrishnan

IPC: H01L27/108 ,  H01L29/786 ,  H01L45/00 ,  H01L49/00 ,  G11C11/22 ,  H01L27/11502

Abstract: Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.