公开(公告)号：US20230026960A1

公开(公告)日：2023-01-26

申请号：US17956797

申请日：2022-09-29

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

IPC: H01L23/00 ,  H01L25/18

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

公开(公告)号：US20220165701A1

公开(公告)日：2022-05-26

申请号：US17103834

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

IPC: H01L23/00 ,  H01L25/18

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

公开(公告)号：US11450645B2

公开(公告)日：2022-09-20

申请号：US17103486

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal

IPC: H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.

公开(公告)号：US11876068B2

公开(公告)日：2024-01-16

申请号：US17956797

申请日：2022-09-29

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

IPC: H01L23/00 ,  H01L25/18

CPC classification number: H01L24/49 ,  H01L24/06 ,  H01L25/18 ,  H01L2924/15165

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

公开(公告)号：US11502053B2

公开(公告)日：2022-11-15

申请号：US17103834

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

IPC: H01L23/00 ,  H01L25/18

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

公开(公告)号：US20220328456A1

公开(公告)日：2022-10-13

申请号：US17850992

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.

公开(公告)号：US20220165708A1

公开(公告)日：2022-05-26

申请号：US17103486

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.