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    METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING LINERS
    1.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING LINERS 有权

    公开(公告)号：US20250159944A1

    公开(公告)日：2025-05-15

    申请号：US19022308

    申请日：2025-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Christopher J. Larsen ,  David A. Daycock ,  Kunal Shrotri

    IPC: H10D30/68 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3213 ,  H10B41/00 ,  H10B41/30 ,  H10B41/60 ,  H10D62/10 ,  H10D64/01

    Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND MEMORY DEVICES
    2.
    发明申请
    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND MEMORY DEVICES 有权

    公开(公告)号：US20250078911A1

    公开(公告)日：2025-03-06

    申请号：US18745943

    申请日：2024-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Haitao Liu ,  David A. Daycock

    IPC: G11C11/4097 ,  G11C11/408 ,  G11C11/4091 ,  H10B12/00

    Abstract: A microelectronic device includes memory cells, hieratical digit line (HDL) structures, and sense amplifier (SA) devices. The memory cells are within an array region and respectively include an access device and a storage node device vertically underlying and coupled to the access device. The HDL structures are within the array region and vertically overlie and are coupled to the memory cells. The HDL structures respectively include a lower section, an upper section vertically overlying and at least partially horizontally offset from the lower section, and a middle section vertically extending from and between the lower section and the upper section. The SA devices are within the array region and vertically overlie and are coupled to the HDL structures. Related methods, memory devices, and electronic systems are also described.

    Methods of forming electronic devices, and related electronic devices
    3.
    发明授权
    Methods of forming electronic devices, and related electronic devices 有权

    公开(公告)号：US11744086B2

    公开(公告)日：2023-08-29

    申请号：US17171622

    申请日：2021-02-09

    Applicant: Micron Technology, Inc.

    Inventor： David A. Daycock ,  Jonghun Kim

    IPC: H10B63/00 ,  H10N70/00

    CPC classification number: H10B63/84 ,  H10N70/023 ,  H10N70/026 ,  H10N70/8265 ,  H10N70/881

    Abstract: A method of forming an electronic device comprises forming a stack structure comprising vertically alternating insulative structures and additional insulative structures, and forming pillars comprising a channel material and at least one dielectric material vertically extending through the stack structure. The method comprises removing the additional insulative structures to form cell openings, forming a first conductive material within a portion of the cell openings, and forming a fill material adjacent to the first conductive material and within the cell openings. The fill material comprises sacrificial portions. The method comprises removing the sacrificial portions of the fill material, and forming a second conductive material within the cell openings in locations previously occupied by the sacrificial portions of the fill material. Related electronic devices, memory devices, and systems are also described.

    BOND PAD CONNECTION LAYOUT
    4.
    发明申请
    BOND PAD CONNECTION LAYOUT 有权

    公开(公告)号：US20230026960A1

    公开(公告)日：2023-01-26

    申请号：US17956797

    申请日：2022-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

    IPC: H01L23/00 ,  H01L25/18

    Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

    SEMICONDUCTOR DEVICES AND STRUCTURES
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND STRUCTURES 审中-公开
    半导体器件和结构

    公开(公告)号：US20160027882A1

    公开(公告)日：2016-01-28

    申请号：US14875493

    申请日：2015-10-05

    Applicant: Micron Technology, Inc.

    Inventor： Christopher J. Larsen ,  David A. Daycock ,  Kunal Shrotri

    IPC: H01L29/423 ,  H01L29/788 ,  H01L29/06 ,  H01L27/115

    CPC classification number: H01L29/42324 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/40114 ,  H01L29/788

    Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

    Abstract translation: 形成半导体器件，存储器单元和存储器单元阵列的方法包括在导电材料上形成衬垫并将衬套暴露于自由基氧化工艺以使衬垫致密化。 致密的衬垫可以保护导电材料在随后的图案化工艺期间免受实质的劣化或损坏。 根据本公开的实施例的半导体器件结构包括从衬底延伸并由暴露衬底的一部分的沟槽间隔开的特征。 衬垫设置在每个特征中的至少一个导电材料的区域的侧壁上。 根据本公开的实施例的半导体器件包括存储器单元，每个存储器单元包括控制栅极区域和具有基本对准侧壁的封盖区域和在控制栅极区域下方的电荷结构。

    BOND PAD CONNECTION LAYOUT
    9.
    发明申请
    BOND PAD CONNECTION LAYOUT 有权

    公开(公告)号：US20220165701A1

    公开(公告)日：2022-05-26

    申请号：US17103834

    申请日：2020-11-24

    Applicant: Micron Technology, Inc.

    Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

    IPC: H01L23/00 ,  H01L25/18

    Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

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