公开(公告)号：US20220404968A1

公开(公告)日：2022-12-22

申请号：US17726255

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Bo Zhou ,  Qilin Pan

IPC: G06F3/06 ,  G06F1/28

Abstract: Methods, systems, and devices for read performance techniques for time retention are described. A memory system may store data in a block of memory cells and perform a power cycle operation. Based on performing the power cycle operation, the memory system may determine a first voltage offset associated with the block of memory cells by executing a first read command using an auto-read calibration operation. Based on the first voltage offset, and, in some examples, one or more additional voltage offsets, the memory system may calculate a retention time of data stored in the block of memory cells. The memory system may adjust a read voltage based on the retention time and perform one or more additional read commands.

公开(公告)号：US20250013374A1

公开(公告)日：2025-01-09

申请号：US18766256

申请日：2024-07-08

Applicant: Micron Technology, Inc.

Inventor： Bo Zhou ,  Qilin Pan

IPC: G06F3/06 ,  G06F1/28

Abstract: Methods, systems, and devices for read performance techniques for time retention are described. A memory system may store data in a block of memory cells and perform a power cycle operation. Based on performing the power cycle operation, the memory system may determine a first voltage offset associated with the block of memory cells by executing a first read command using an auto-read calibration operation. Based on the first voltage offset, and, in some examples, one or more additional voltage offsets, the memory system may calculate a retention time of data stored in the block of memory cells. The memory system may adjust a read voltage based on the retention time and perform one or more additional read commands.

公开(公告)号：US12050794B2

公开(公告)日：2024-07-30

申请号：US17726255

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Bo Zhou ,  Qilin Pan

IPC: G06F12/00 ,  G06F1/28 ,  G06F3/06

CPC classification number: G06F3/064 ,  G06F1/28 ,  G06F3/0614 ,  G06F3/0673

Abstract: Methods, systems, and devices for read performance techniques for time retention are described. A memory system may store data in a block of memory cells and perform a power cycle operation. Based on performing the power cycle operation, the memory system may determine a first voltage offset associated with the block of memory cells by executing a first read command using an auto-read calibration operation. Based on the first voltage offset, and, in some examples, one or more additional voltage offsets, the memory system may calculate a retention time of data stored in the block of memory cells. The memory system may adjust a read voltage based on the retention time and perform one or more additional read commands.