公开(公告)号：US20250085887A1

公开(公告)日：2025-03-13

申请号：US18777273

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Srivatsan Venkatesan ,  Kaveri Jain ,  Salil Shashikant Mujumdar ,  Rajat Vishnoi ,  Sushma Dogiparthi

IPC: G06F3/06 ,  G11C16/04

Abstract: An inductor is formed on an integrated circuit (IC) using one or more structures formed during or in coordination with 3D NAND structure fabrication with one or more modifications. The inductor has a staircase structure, the staircase structure having a plurality of tiers that form steps on one side of the staircase structure. Each tier comprises a conductive layer. The plurality of tiers includes at least a first tier and a second tier. The inductor has a first contact electrically coupling the first tier and the second tier. A first portion of a die is occupied by a memory sub-component comprising at least one three-dimensional (3D) NAND memory component and a second portion of the die is occupied by the inductor.