公开(公告)号：US20180366406A1

公开(公告)日：2018-12-20

申请号：US16042255

申请日：2018-07-23

Applicant: Micron Technology, Inc.

Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue (Gloria) Chen ,  Anton J. deVilliers

IPC: H01L23/528 ,  H01L21/467 ,  H01L23/52 ,  H01L21/768 ,  H01L21/027 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.

公开(公告)号：US20140299971A1

公开(公告)日：2014-10-09

申请号：US14312945

申请日：2014-06-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveri Jain ,  Anton J. deVilliers

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  G03F7/2022 ,  Y10T428/24802

Abstract: A method of forming a reversed pattern in a substrate. A resist on a substrate is exposed and developed to form a pattern therein, the patterned resist having a first polarity. The polarity of the patterned resist is reversed to a second polarity, and a reversal film is formed over the patterned resist having the second polarity. The patterned resist having the second polarity is removed, forming a pattern in the reversal film. The pattern in the reversal film is then transferred to the substrate. Additional methods of forming a reversed pattern in a substrate are disclosed, as is a semiconductor structure formed during the methods.

Abstract translation: 在基板中形成反转图案的方法。 衬底上的抗蚀剂被曝光和显影以在其中形成图案，图案化抗蚀剂具有第一极性。 图案化抗蚀剂的极性反转到第二极性，并且在具有第二极性的图案化抗蚀剂上形成反转膜。 去除具有第二极性的图案化抗蚀剂，在反转膜中形成图案。 然后将反转膜中的图案转移到基底。 公开了在衬底中形成反向图案的附加方法，以及在该方法期间形成的半导体结构。

公开(公告)号：US20130302981A1

公开(公告)日：2013-11-14

申请号：US13941747

申请日：2013-07-15

Applicant: Micron Technology, Inc.

Inventor： Dan Millward ,  Kaveri Jain ,  Zishu Zhang ,  Lijing Gou ,  Anton J. deVilliers ,  Jianming Zhou ,  Yuan He ,  Michael D. Hyatt ,  Scott L. Light

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10888

Abstract: Some embodiments include methods of forming patterns. A semiconductor substrate is formed to comprise an electrically insulative material over a set of electrically conductive structures. An interconnect region is defined across the electrically conductive structures, and regions on opposing sides of the interconnect region are defined as secondary regions. A two-dimensional array of features is formed over the electrically insulative material. The two-dimensional array extends across the interconnect region and across the secondary regions. A pattern of the two-dimensional array is transferred through the electrically insulative material of the interconnect region to form contact openings that extend through the electrically insulative material and to the electrically conductive structures, and no portions of the two-dimensional array of the secondary regions is transferred into the electrically insulative material.

Abstract translation: 一些实施例包括形成图案的方法。 半导体衬底被形成为在一组导电结构之上包括电绝缘材料。 跨导电结构限定互连区域，并且互连区域的相对侧上的区域被定义为次级区域。 特征的二维阵列形成在电绝缘材料上。 二维阵列跨越互连区域并跨越次级区域延伸。 二维阵列的图案通过互连区域的电绝缘材料转移以形成延伸穿过电绝缘材料和导电结构的接触开口，并且二次区域的二维阵列的任何部分 被转移到电绝缘材料中。

公开(公告)号：US20130252142A1

公开(公告)日：2013-09-26

申请号：US13892711

申请日：2013-05-13

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Kaveri Jain ,  Lijing Gou ,  Zishu Zhang ,  Anton J. deVilliers ,  Michael Hyatt ,  Jianming Zhou ,  Scott L. Light ,  Dan B. Millward

IPC: G03F1/38

CPC classification number: G03F1/38 ,  G03F1/50 ,  G03F1/54 ,  Y10T29/49002

Abstract: An imaging device comprising a first region and a second region. Imaging features in the first region and assist features in the second region are substantially the same size as one another and are formed substantially on pitch. Methods of forming an imaging device and methods of forming a semiconductor device structure are also disclosed.

Abstract translation: 一种成像装置，包括第一区域和第二区域。 第一区域中的成像特征和第二区域中的辅助特征基本上彼此相同，并且基本上在间距上形成。 还公开了形成成像装置的方法和形成半导体器件结构的方法。

公开(公告)号：US20240297124A1

公开(公告)日：2024-09-05

申请号：US18593504

申请日：2024-03-01

Applicant: Micron Technology, Inc.

Inventor： Shruthi Kumara Vadivel ,  Harsh Narendrakumar Jain ,  Lance David Williamson ,  Kaveri Jain ,  Adam Lewis Olson

IPC: H01L23/544 ,  H01L21/308

CPC classification number: H01L23/544 ,  H01L21/308 ,  H01L2223/54426

Abstract: A memory device can include a substrate and a first alignment mark embedded in the substrate. The first alignment mark can be configured to a reference for a patterned second masking layer which is different from a first masking layer deposited on the substrate, and onto which the second patterned masking layer is deposited. The first masking layer can be an opaque or semi-opaque sacrificial layer and a second alignment mark can comprise at least a portion of the first masking layer. A location of the second alignment mark can correspond to a particular structure location in the substrate. The patterned second masking layer can include an additional alignment mark that is spaced laterally apart from the second alignment mark and the patterned second masking layer can define one or more locations of one or more structural features in the substrate.

公开(公告)号：US10147638B1

公开(公告)日：2018-12-04

申请号：US15858072

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Lance Williamson ,  Adam L. Olson ,  Kaveri Jain ,  Robert Dembi ,  William R. Brown

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556

Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

公开(公告)号：US20170263552A1

公开(公告)日：2017-09-14

申请号：US15606312

申请日：2017-05-26

Applicant: Micron Technology, Inc.

Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue (Gloria) Chen ,  Anton J. deVilliers

IPC: H01L23/528 ,  H01L21/027 ,  H01L23/52 ,  H01L21/467 ,  H01L21/308 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.

公开(公告)号：US09177795B2

公开(公告)日：2015-11-03

申请号：US14040245

申请日：2013-09-27

Applicant: Micron Technology, Inc.

Inventor： Nicholas Hendricks ,  Adam L. Olson ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Kaveri Jain ,  Scott Schuldenfrei

IPC: H01L21/302 ,  H01L21/027 ,  C08G81/00

CPC classification number: H01L21/0273 ,  B81C1/00031 ,  B81C2201/0149 ,  C08G81/00 ,  C08L53/005 ,  H01L21/02118 ,  H01L21/02175 ,  H01L21/02318 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31058

Abstract: A method of forming nanostructures may include forming a block copolymer composition within a trench in a material on a substrate, wherein the block copolymer composition may comprise a block copolymer material and an activatable catalyst having a higher affinity for a first block of the block copolymer material compared to a second block of the block copolymer material; self-assembling the block copolymer composition into first domains comprising the first block and the activatable catalyst, and second domains comprising the second block; generating catalyst from the activatable catalyst in at least one portion of the first domains to produce a structure comprising catalyst-containing domains and the second domains, the catalyst-containing domains comprising the first block and the catalyst; and reacting a metal oxide precursor with the catalyst in the catalyst-containing domains to produce a metal oxide-containing structure comprising the first block and metal oxide.

Abstract translation: 形成纳米结构的方法可以包括在衬底中的材料中的沟槽内形成嵌段共聚物组合物，其中嵌段共聚物组合物可以包含嵌段共聚物材料和对于嵌段共聚物材料的第一嵌段具有更高亲和力的可活化催化剂 与第二嵌段共聚物材料相比; 将嵌段共聚物组合物自组装成包含第一嵌段和可活化催化剂的第一畴，以及包含第二嵌段的第二畴; 在第一区域的至少一部分中从可活化催化剂产生催化剂以产生包含含催化剂的区域和第二区域的结构，所述含催化剂的区域包含第一嵌段和催化剂; 并使金属氧化物前体与含催化剂的区域中的催化剂反应，以制备包含第一嵌段和金属氧化物的含金属氧化物的结构。

公开(公告)号：US20150179467A1

公开(公告)日：2015-06-25

申请号：US14139582

申请日：2013-12-23

Applicant: Micron Technology, Inc. ,  Rohm and Haas Electronic Materials LLC ,  Dow Global Technologies LLC

Inventor： William R. Brown ,  Adam Olson ,  Kaveri Jain ,  Ho Seop Eom ,  Xue Gloria Chen ,  Nik Mirin ,  Dan Millward ,  Peter Trefonas, III ,  Phillip Dene Hustad ,  Jong Keun Park ,  Christopher Nam Lee

IPC: H01L21/308

CPC classification number: H01L21/0274 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

Abstract: Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first pattern. The first pattern has a first level of uniformity across a distribution of the features. A brush layer is formed across the first mask and within the features to narrow the features and create a second mask from the first mask. The second mask has a second level of uniformity across the narrowed features which is greater than the first level of uniformity. A pattern is transferred from the second mask into the material.

Abstract translation: 一些实施例包括形成图案的方法。 在材料上形成第一个掩模。 第一掩模具有在其中延伸的特征并且限定第一图案。 第一种模式在特征分布上具有第一级的均匀性。 在第一掩模之间并且在特征内形成刷层以使特征变窄以从第一掩模创建第二掩模。 所述第二掩模具有比所述第一级别的均匀性更窄的所述窄化特征的第二级别的均匀性。 图案从第二个掩模转移到材料中。

公开(公告)号：US20150091137A1

公开(公告)日：2015-04-02

申请号：US14040245

申请日：2013-09-27

Applicant: Micron Technology, Inc.

Inventor： Nicholas Hendricks ,  Adam L. Olson ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Kaveri Jain ,  Scott Schuldenfrei

IPC: H01L21/027 ,  C08G81/00

CPC classification number: H01L21/0273 ,  B81C1/00031 ,  B81C2201/0149 ,  C08G81/00 ,  C08L53/005 ,  H01L21/02118 ,  H01L21/02175 ,  H01L21/02318 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31058

Abstract: A method of forming nanostructures may include forming a block copolymer composition within a trench in a material on a substrate, wherein the block copolymer composition may comprise a block copolymer material and an activatable catalyst having a higher affinity for a first block of the block copolymer material compared to a second block of the block copolymer material; self-assembling the block copolymer composition into first domains comprising the first block and the activatable catalyst, and second domains comprising the second block; generating catalyst from the activatable catalyst in at least one portion of the first domains to produce a structure comprising catalyst-containing domains and the second domains, the catalyst-containing domains comprising the first block and the catalyst; and reacting a metal oxide precursor with the catalyst in the catalyst-containing domains to produce a metal oxide-containing structure comprising the first block and metal oxide.

Abstract translation: 形成纳米结构的方法可以包括在衬底中的材料中的沟槽内形成嵌段共聚物组合物，其中嵌段共聚物组合物可以包含嵌段共聚物材料和对于嵌段共聚物材料的第一嵌段具有更高亲和力的可活化催化剂 与第二嵌段共聚物材料相比; 将嵌段共聚物组合物自组装成包含第一嵌段和可活化催化剂的第一畴，以及包含第二嵌段的第二畴; 在第一区域的至少一部分中从可活化催化剂产生催化剂以产生包含含催化剂的区域和第二区域的结构，所述含催化剂的区域包含第一嵌段和催化剂; 并使金属氧化物前体与含催化剂的区域中的催化剂反应，以制备包含第一嵌段和金属氧化物的含金属氧化物的结构。