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公开(公告)号：US20220164269A1
公开(公告)日：2022-05-26
申请号：US16953828
申请日：2020-11-20
Applicant: Micron Technology, Inc.
Inventor： Sang-Hoon Shin , Won Joo Yun , Rajesh H. Kariya
Abstract: Test input/output speed conversion and related apparatuses and methods are disclosed. An apparatus includes a glue circuit and a BIST circuit for core circuitry of an integrated circuit device. The, the BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glue circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glue circuit is configured to convert between second speed test interface signals and second speed input/output signals operating at a second speed and first speed test interface signals and first speed input/output signals operating at the first speed. The second speed is different from the first speed.
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公开(公告)号：US11886376B2
公开(公告)日：2024-01-30
申请号：US17398863
申请日：2021-08-10
Applicant: Micron Technology, Inc.
Inventor： Won Joo Yun , Sang-Hoon Shin
CPC classification number: G06F15/7871 , G06F15/7892 , G11C7/1057 , G11C7/1084
Abstract: An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. An reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.
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Patent Agency Ranking
公开(公告)号：US11789835B2
公开(公告)日：2023-10-17
申请号：US16953828
申请日：2020-11-20
Applicant: Micron Technology, Inc.
Inventor： Sang-Hoon Shin , Won Joo Yun , Rajesh H. Kariya
Abstract: Test input/output speed conversion and related apparatuses and methods are disclosed. An apparatus includes a glue circuit and a BIST circuit for core circuitry of an integrated circuit device. The, the BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glue circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glue circuit is configured to convert between second speed test interface signals and second speed input/output signals operating at a second speed and first speed test interface signals and first speed input/output signals operating at the first speed. The second speed is different from the first speed.
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公开(公告)号：US20230051183A1
公开(公告)日：2023-02-16
申请号：US17398863
申请日：2021-08-10
Applicant: Micron Technology, Inc.
Inventor： Won Joo Yun , Sang-Hoon Shin
Abstract: An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. An reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.
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公开(公告)号：US11500575B2
公开(公告)日：2022-11-15
申请号：US17029718
申请日：2020-09-23
Applicant: Micron Technology, Inc.
Inventor： Sang-Hoon Shin
IPC: G06F3/06
Abstract: Methods, systems, and devices for pattern generation for multi-channel memory array are described. A device may include a memory array and a circuit for testing the memory array. The memory array may include a first set of memory cells and a second set of memory cells, the first set of memory cells coupled with a first channel and the second set of memory cells coupled with a second channel. The circuit may be coupled with the memory array and may include a pattern generator and an output response analyzer. The pattern generator may be configured to selectively output a single pattern when operating in a single-pattern mode or a plurality of patterns when operating in a multi-pattern mode. The output response analyzer configured to determine whether the memory array includes one or more errors based at least in part on a pattern output by the pattern generator.
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公开(公告)号：US20240160600A1
公开(公告)日：2024-05-16
申请号：US18421686
申请日：2024-01-24
Applicant: Micron Technology, Inc.
Inventor： Won Joo Yun , Sang-Hoon Shin
CPC classification number: G06F15/7871 , G06F15/7892 , G11C7/1057 , G11C7/1084
Abstract: An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. A reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.
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公开(公告)号：US20220091776A1
公开(公告)日：2022-03-24
申请号：US17029718
申请日：2020-09-23
Applicant: Micron Technology, Inc.
Inventor： Sang-Hoon Shin
IPC: G06F3/06
Abstract: Methods, systems, and devices for pattern generation for multi-channel memory array are described. A device may include a memory array and a circuit for testing the memory array. The memory array may include a first set of memory cells and a second set of memory cells, the first set of memory cells coupled with a first channel and the second set of memory cells coupled with a second channel. The circuit may be coupled with the memory array and may include a pattern generator and an output response analyzer. The pattern generator may be configured to selectively output a single pattern when operating in a single-pattern mode or a plurality of patterns when operating in a multi-pattern mode. The output response analyzer configured to determine whether the memory array includes one or more errors based at least in part on a pattern output by the pattern generator.
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