公开(公告)号：US20220164269A1

公开(公告)日：2022-05-26

申请号：US16953828

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Sang-Hoon Shin ,  Won Joo Yun ,  Rajesh H. Kariya

IPC: G06F11/27 ,  G06F13/20 ,  G06F1/12

Abstract: Test input/output speed conversion and related apparatuses and methods are disclosed. An apparatus includes a glue circuit and a BIST circuit for core circuitry of an integrated circuit device. The, the BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glue circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glue circuit is configured to convert between second speed test interface signals and second speed input/output signals operating at a second speed and first speed test interface signals and first speed input/output signals operating at the first speed. The second speed is different from the first speed.

公开(公告)号：US11488879B2

公开(公告)日：2022-11-01

申请号：US16896120

申请日：2020-06-08

Applicant: Micron Technology, Inc.

Inventor： Rajesh H. Kariya ,  Boon Hor Lam

IPC: G11C29/38 ,  H01L21/66

Abstract: Wafer-level testing of multiple adjacent semiconductor die of a semiconductor wafer in parallel using built-in self-test circuitry for a memory (mBIST) and scribe lines that connect certain terminals of a semiconductor die to terminals of an adjacent semiconductor die. During the wafer-level testing, probe needles of a test setup connect to a single one of the multiple adjacent semiconductor die, and mBIST commands are passed from the single one of the multiple adjacent semiconductor die to one or more adjacent semiconductor die. In some examples, the scribe lines connect mBIST circuit terminals of one semiconductor die to mBIST circuit terminals of an adjacent semiconductor die. In some examples, the scribe lines connect I/O terminals of one semiconductor die to I/O terminals of an adjacent semiconductor die. The scribe lines may cross scribe regions of the wafer to connect the respective terminals of the adjacent semiconductor die.

公开(公告)号：US11789835B2

公开(公告)日：2023-10-17

申请号：US16953828

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Sang-Hoon Shin ,  Won Joo Yun ,  Rajesh H. Kariya

IPC: G06F11/27 ,  G06F1/00 ,  G06F13/00 ,  G06F1/12 ,  G06F13/20

CPC classification number: G06F11/27 ,  G06F1/12 ,  G06F13/20

Abstract: Test input/output speed conversion and related apparatuses and methods are disclosed. An apparatus includes a glue circuit and a BIST circuit for core circuitry of an integrated circuit device. The, the BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glue circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glue circuit is configured to convert between second speed test interface signals and second speed input/output signals operating at a second speed and first speed test interface signals and first speed input/output signals operating at the first speed. The second speed is different from the first speed.

公开(公告)号：US20240231459A1

公开(公告)日：2024-07-11

申请号：US18400614

申请日：2023-12-29

Applicant: Micron Technology, Inc.

Inventor： Rajesh H. Kariya

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: Methods, systems, and devices for power management and delivery for high bandwidth memory are described. A high bandwidth memory (HBM) device may include a power management integrated circuit (PMIC) and a voltage regulator integrated within an interface die of the HBM system or included as a separate chip within the HBM system stack. Accordingly, the HBM system may be supplied a higher voltage and may regulate the voltage to a desired power level, which may increase the total power available to the HBM system without increasing the quantity of microbumps. Additionally, a ground voltage, a positive voltage, or both, may be supplied to the HBM device via a back interface of the HBM device, which may reduce the quantity of microbumps at a front interface. In some examples, a modified heatsink assembly may supply the ground voltage, the positive voltage, or both, to the HBM system.

公开(公告)号：US20210202328A1

公开(公告)日：2021-07-01

申请号：US16896120

申请日：2020-06-08

Applicant: Micron Technology, Inc.

Inventor： Rajesh H. Kariya ,  Boon Hor Lam

IPC: H01L21/66 ,  G11C29/38

Abstract: Wafer-level testing of multiple adjacent semiconductor die of a semiconductor wafer in parallel using built-in self-test circuitry for a memory (mBIST) and scribe lines that connect certain terminals of a semiconductor die to terminals of an adjacent semiconductor die. During the wafer-level testing, probe needles of a test setup connect to a single one of the multiple adjacent semiconductor die, and mBIST commands are passed from the single one of the multiple adjacent semiconductor die to one or more adjacent semiconductor die. In some examples, the scribe lines connect mBIST circuit terminals of one semiconductor die to mBIST circuit terminals of an adjacent semiconductor die. In some examples, the scribe lines connect I/O terminals of one semiconductor die to I/O terminals of an adjacent semiconductor die. The scribe lines may cross scribe regions of the wafer to connect the respective terminals of the adjacent semiconductor die.