公开(公告)号：US11263123B2

公开(公告)日：2022-03-01

申请号：US17080495

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Kyle B. Wheeler ,  Richard C. Murphy

IPC: G06F12/02 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096 ,  G06F12/0888 ,  G06F15/78 ,  G11C8/12

Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.

公开(公告)号：US20210110858A1

公开(公告)日：2021-04-15

申请号：US17107463

申请日：2020-11-30

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny

IPC: G11C11/402 ,  G11C11/406 ,  G11C11/403 ,  G11C5/02 ,  G11C7/10 ,  G11C11/407

Abstract: The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.

公开(公告)号：US10817414B2

公开(公告)日：2020-10-27

申请号：US16224498

申请日：2018-12-18

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Kyle B. Wheeler ,  Richard C. Murphy

IPC: G06F12/02 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096 ,  G06F12/0888 ,  G06F15/78 ,  G11C8/12

Abstract: The apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.

公开(公告)号：US10522199B2

公开(公告)日：2019-12-31

申请号：US15669300

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Kelley D. Dobelstein ,  Timothy P. Finkbeiner ,  Richard C. Murphy

IPC: G11C7/10 ,  G11C7/06 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

公开(公告)号：US20180240509A1

公开(公告)日：2018-08-23

申请号：US15961374

申请日：2018-04-24

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Glen E. Hush

IPC: G11C11/4091 ,  G11C16/28 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C7/1006 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  G11C16/28 ,  G11C2211/4013

Abstract: Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.

公开(公告)号：US09959923B2

公开(公告)日：2018-05-01

申请号：US15098707

申请日：2016-04-14

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Glen E. Hush

IPC: G11C7/00 ,  G11C11/4091 ,  G11C16/28 ,  G11C11/408 ,  G11C11/4097 ,  G11C7/10 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C7/1006 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  G11C16/28 ,  G11C2211/4013

Abstract: Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.

公开(公告)号：US20170336989A1

公开(公告)日：2017-11-23

申请号：US15669538

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner

IPC: G06F3/06 ,  G11C8/12 ,  G11C7/10 ,  G11C29/28 ,  G11C29/26

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0683 ,  G06F15/7821 ,  G11C5/025 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12 ,  G11C29/28 ,  G11C2029/2602

Abstract: The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

公开(公告)号：US20210390988A1

公开(公告)日：2021-12-16

申请号：US17461084

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Kelley D. Dobelstein ,  Jason T. Zawodny ,  Kyle B. Wheeler

IPC: G11C7/10 ,  G11C11/4076 ,  G11C11/4074 ,  G06F12/06 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4096 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.

公开(公告)号：US20210217449A1

公开(公告)日：2021-07-15

申请号：US17215581

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Kelley D. Dobelstein ,  Timothy P. Finkbeiner ,  Richard C. Murphy

IPC: G11C7/10 ,  G11C8/12 ,  G11C11/4096 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/408 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

公开(公告)号：US10942652B2

公开(公告)日：2021-03-09

申请号：US16433803

申请日：2019-06-06

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner

IPC: G06F3/06 ,  G11C7/10 ,  G11C8/12 ,  G06F15/78 ,  G11C29/28 ,  G11C29/26 ,  G11C5/02

Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to pre-resolved instructions. An example apparatus comprises a memory device coupled to a host via a data bus and a control bus. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes sense amplifiers and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of address translated instructions and/or constant data from the host. The memory controller is configured to write the address translated instructions and/or constant data to a plurality of locations in a bank of the memory device in parallel.