公开(公告)号：US11698862B2

公开(公告)日：2023-07-11

申请号：US17382953

申请日：2021-07-22

申请人： Micron Technology, Inc.

发明人： Vijay S. Ramesh ,  Anton Korzh ,  Richard C. Murphy ,  Scott Matthew Stephens

IPC分类号： G06F12/02 ,  G06F12/0811 ,  G06F3/06

CPC分类号： G06F12/0811 ,  G06F12/0246 ,  G06F3/0656 ,  G06F2212/1016 ,  G06F2212/305 ,  G06F2212/608

摘要： Systems, apparatuses, and methods related to three tiered hierarchical memory systems are described herein. A three tiered hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example apparatus may include a persistent memory, and one or more non-persistent memories configured to map an address associated with an input/output (I/O) device to an address in logic circuitry prior to the apparatus receiving a request from the I/O device to access data stored in the persistent memory, and map the address associated with the I/O device to an address in a non-persistent memory subsequent to the apparatus receiving the request and accessing the data.

公开(公告)号：US20210056025A1

公开(公告)日：2021-02-25

申请号：US16547635

申请日：2019-08-22

申请人： Micron Technology, Inc.

发明人： Vijay S. Ramesh ,  Anton Korzh ,  Richard C. Murphy ,  Scott Matthew Stephens

IPC分类号： G06F12/0811

摘要： Systems, apparatuses, and methods related to three tiered hierarchical memory systems are described herein. A three tiered hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example apparatus may include a persistent memory, and one or more non-persistent memories configured to map an address associated with an input/output (I/O) device to an address in logic circuitry prior to the apparatus receiving a request from the I/O device to access data stored in the persistent memory, and map the address associated with the I/O device to an address in a non-persistent memory subsequent to the apparatus receiving the request and accessing the data.

公开(公告)号：US20210349822A1

公开(公告)日：2021-11-11

申请号：US17382953

申请日：2021-07-22

申请人： Micron Technology, Inc.

发明人： Vijay S. Ramesh ,  Anton Korzh ,  Richard C. Murphy ,  Scott Matthew Stephens

IPC分类号： G06F12/0811 ,  G06F12/02

摘要： Systems, apparatuses, and methods related to three tiered hierarchical memory systems are described herein. A three tiered hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example apparatus may include a persistent memory, and one or more non-persistent memories configured to map an address associated with an input/output (1/0) device to an address in logic circuitry prior to the apparatus receiving a request from the I/O device to access data stored in the persistent memory, and map the address associated with the I/O device to an address in a non-persistent memory subsequent to the apparatus receiving the request and accessing the data.

公开(公告)号：US11074182B2

公开(公告)日：2021-07-27

申请号：US16547635

申请日：2019-08-22

申请人： Micron Technology, Inc.

发明人： Vijay S. Ramesh ,  Anton Korzh ,  Richard C. Murphy ,  Scott Matthew Stephens

IPC分类号： G06F12/02 ,  G06F12/0811 ,  G06F3/06

摘要： Systems, apparatuses, and methods related to three tiered hierarchical memory systems are described herein. A three tiered hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example apparatus may include a persistent memory, and one or more non-persistent memories configured to map an address associated with an input/output (I/O) device to an address in logic circuitry prior to the apparatus receiving a request from the I/O device to access data stored in the persistent memory, and map the address associated with the I/O device to an address in a non-persistent memory subsequent to the apparatus receiving the request and accessing the data.