公开(公告)号：US11755210B2

公开(公告)日：2023-09-12

申请号：US17665307

申请日：2022-02-04

申请人： Micron Technology, Inc.

发明人： Richard C. Murphy ,  Shivam Swami ,  Naveh Malihi ,  Anton Korzh ,  Glen E. Hush

IPC分类号： G06F3/06

CPC分类号： G06F3/0622 ,  G06F3/0638 ,  G06F3/0655 ,  G06F3/0673

摘要： Apparatuses and methods related to mitigating unauthorized memory access are described. Mitigating unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then a row of the memory array corresponding to the access command may not be activated.

公开(公告)号：US11698862B2

公开(公告)日：2023-07-11

申请号：US17382953

申请日：2021-07-22

申请人： Micron Technology, Inc.

发明人： Vijay S. Ramesh ,  Anton Korzh ,  Richard C. Murphy ,  Scott Matthew Stephens

IPC分类号： G06F12/02 ,  G06F12/0811 ,  G06F3/06

CPC分类号： G06F12/0811 ,  G06F12/0246 ,  G06F3/0656 ,  G06F2212/1016 ,  G06F2212/305 ,  G06F2212/608

摘要： Systems, apparatuses, and methods related to three tiered hierarchical memory systems are described herein. A three tiered hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example apparatus may include a persistent memory, and one or more non-persistent memories configured to map an address associated with an input/output (I/O) device to an address in logic circuitry prior to the apparatus receiving a request from the I/O device to access data stored in the persistent memory, and map the address associated with the I/O device to an address in a non-persistent memory subsequent to the apparatus receiving the request and accessing the data.

公开(公告)号：US20210255807A1

公开(公告)日：2021-08-19

申请号：US17307873

申请日：2021-05-04

申请人： Micron Technology, Inc.

发明人： Anton Korzh ,  Vijay S. Ramesh ,  Richard C. Murphy

IPC分类号： G06F3/06 ,  G06F13/38 ,  G06F9/455 ,  G06F9/30

摘要： Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.

公开(公告)号：US20210055884A1

公开(公告)日：2021-02-25

申请号：US16547837

申请日：2019-08-22

申请人： Micron Technology, Inc.

发明人： Anton Korzh ,  Vijay S. Ramesh ,  Richard C. Murphy

IPC分类号： G06F3/06 ,  G06F13/38 ,  G06F9/30 ,  G06F9/455

摘要： Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.

公开(公告)号：US10691593B1

公开(公告)日：2020-06-23

申请号：US16226244

申请日：2018-12-19

申请人： Micron Technology, Inc.

发明人： Anton Korzh

IPC分类号： G06F12/10 ,  G06F12/0802 ,  G06N20/00 ,  G06F3/06

摘要： Techniques for implementing an apparatus, which includes a memory system that provides data storage via multiple hierarchical memory levels, are provided. The memory system includes a cache that implements a first memory level and a memory array that implements a second memory level higher than the first memory level. Additionally, the memory system includes one or more memory controllers that determine a predicted data access pattern expected to occur during an upcoming control horizon, based at least in part on first context of first data to be stored in the memory sub-system, second context of second data previously stored in the memory system, or both, and control what one or more memory levels of the multiple hierarchical memory levels implemented in the memory system in which to store the first data, the second data, or both based at least in part on the predicted data access pattern.

公开(公告)号：US10691347B2

公开(公告)日：2020-06-23

申请号：US16053584

申请日：2018-08-02

申请人： MICRON TECHNOLOGY, INC.

发明人： Richard C. Murphy ,  Anton Korzh ,  Stephen S. Pawlowski

IPC分类号： G06F12/0815 ,  G06F3/06 ,  G06F12/0811

摘要： The present disclosure techniques for implementing an apparatus, which includes processing circuitry that performs an operation based a target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple of data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.

公开(公告)号：US20190354303A1

公开(公告)日：2019-11-21

申请号：US16529525

申请日：2019-08-01

申请人： Micron Technology, Inc.

发明人： Jeremiah J. Willcock ,  Perry V. Lea ,  Anton Korzh

IPC分类号： G06F3/06 ,  G06T1/60 ,  G06T1/00 ,  G11C11/4096 ,  G11C7/10 ,  H04N19/186 ,  G11C11/4091

摘要： The present disclosure includes apparatuses and methods for operations using compressed and decompressed data. An example method includes receiving compressed data to a processing in memory (PIM) device and decompressing the compressed data on the PIM device.

公开(公告)号：US11748262B2

公开(公告)日：2023-09-05

申请号：US17411719

申请日：2021-08-25

申请人： Micron Technology, Inc.

发明人： Anton Korzh

IPC分类号： G06F12/08 ,  G06F12/0802 ,  G06N20/00 ,  G06F3/06

CPC分类号： G06F12/0802 ,  G06F3/0626 ,  G06F3/0638 ,  G06F3/0688 ,  G06N20/00

摘要： Techniques for implementing an apparatus, which includes a memory system that provides data storage via multiple hierarchical memory levels, are provided. The memory system includes a cache that implements a first memory level and a memory array that implements a second memory level higher than the first memory level. Additionally, the memory system includes one or more memory controllers that determine a predicted data access pattern expected to occur during an upcoming control horizon, based at least in part on first context of first data to be stored in the memory sub-system, second context of second data previously stored in the memory system, or both, and control what one or more memory levels of the multiple hierarchical memory levels implemented in the memory system in which to store the first data, the second data, or both based at least in part on the predicted data access pattern.

公开(公告)号：US11614894B2

公开(公告)日：2023-03-28

申请号：US17307873

申请日：2021-05-04

申请人： Micron Technology, Inc.

发明人： Anton Korzh ,  Vijay S. Ramesh ,  Richard C. Murphy

IPC分类号： G06F3/00 ,  G06F3/06 ,  G06F13/38 ,  G06F9/455 ,  G06F9/30

摘要： Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.

公开(公告)号：US11579882B2

公开(公告)日：2023-02-14

申请号：US17212330

申请日：2021-03-25

申请人： Micron Technology, Inc.

发明人： Richard C. Murphy ,  Glen E. Hush ,  Vijay S. Ramesh ,  Allan Porterfield ,  Anton Korzh

IPC分类号： G06F9/34 ,  G06F3/06 ,  G06F9/24

摘要： Systems, apparatuses, and methods related to extended memory operations are described. Extended memory operations can include operations specified by a single address and operand and may be performed by a computing device that includes a processing unit and a memory resource. The computing device can perform extended memory operations on data streamed through the computing tile without receipt of intervening commands. In an example, a computing device is configured to receive a command to perform an operation that comprises performing an operation on a data with the processing unit of the computing device and determine that an operand corresponding to the operation is stored in the memory resource. The computing device can further perform the operation using the operand stored in the memory resource.