公开(公告)号：US20240289275A1

公开(公告)日：2024-08-29

申请号：US18566583

申请日：2022-05-16

Applicant: HYGON INFORMATION TECHNOLOGY CO., LTD.

Inventor： Haifeng ZHAI ,  Hang ZUO ,  Sen WANG ,  Yu PAN ,  Chengqiang MEI

IPC: G06F12/0811 ,  G06F12/123

CPC classification number: G06F12/0811 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/305

Abstract: The embodiment of the invention provides a data processing method and apparatus, a cache, a processor and an electronic device. The data processing method includes: receiving a data processing request, wherein data requested by the data processing request includes data that is suitable for being stored in at least two cache units, and main memory addresses of the data in each of the cache units are consecutive; and when main memory address information of each cache unit that satisfies a mapping relationship includes all the main memory addresses, simultaneously performing data processing on the data which corresponds to the main memory addresses. Through the method, a bandwidth is improved such that the efficiency of data transmission is improved.

公开(公告)号：US20230401066A1

公开(公告)日：2023-12-14

申请号：US17835409

申请日：2022-06-08

Applicant: Ventana Micro Systems Inc.

Inventor： John G. Favor ,  Michael N. Michael ,  Vihar Soneji

IPC: G06F9/38 ,  G06F12/0875 ,  G06F12/1045

CPC classification number: G06F9/3806 ,  G06F9/3867 ,  G06F12/0875 ,  G06F12/1054 ,  G06F2212/452 ,  G06F2212/305

Abstract: A dynamically-foldable instruction fetch pipeline receives a first fetch request that includes a fetch virtual address and includes first, second and third sub-pipelines that respectively include a translation lookaside buffer (TLB) that translates the fetch virtual address into a fetch physical address, a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache that receives a set index that selects a set of tag RAM tags for comparison with a tag portion of the fetch physical address to determine a correct way of the instruction cache, and a data RAM of the instruction cache that receives the set index and a way number that together specify a data RAM entry from which to fetch an instruction block. When a control signal indicates a folded mode, the sub-pipelines operate in a parallel manner. When the control signal indicates a unfolded mode, the sub-pipelines operate in a sequential manner.

公开(公告)号：US20230393971A1

公开(公告)日：2023-12-07

申请号：US18451183

申请日：2023-08-17

Applicant: NeuroBlade Ltd.

Inventor： Yoav MARKUS ,  Eliad HILLEL ,  Ilan MAYER-WOLF ,  Yaron KITTNER

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/305

Abstract: A system for distributed storage agents includes at least one memory and at least one compute node comprising at least one agent module. The at least one agent module is configured to cause at least a portion of data stored in the at least one memory to be pushed to a destination in accordance with an agent access plan.

公开(公告)号：US11803471B2

公开(公告)日：2023-10-31

申请号：US17821312

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  Sergio Kolor ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Tal Kuzi ,  Jeffry E. Gonion ,  Charles E. Tucker ,  Lital Levy-Rubin ,  Dany Davidov ,  Steven Fishwick ,  Nir Leshem ,  Mark Pilip ,  Gerard R. Williams, III ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F13/28 ,  G06F13/16 ,  G06F13/40 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/128 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4068 ,  G06F15/17368 ,  G06F15/7807 ,  G06F2212/305 ,  G06F2212/657

Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

公开(公告)号：US20190033949A1

公开(公告)日：2019-01-31

申请号：US15661003

申请日：2017-07-27

Applicant: International Business Machines Corporation

Inventor： Kevin M. Mcilvain ,  Saravanan Sethuraman ,  Warren E. Maule ,  Kyu-hyoun Kim

IPC: G06F1/32 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0635 ,  G06F3/0659 ,  G06F3/0683 ,  G06F9/4405 ,  G06F9/442 ,  G06F2212/3042 ,  G06F2212/305

Abstract: A three-dimensional stacked (3DS) memory module includes multiple memory chips physically integrated with a data I/O chip. The data I/O chip includes multiple data interfaces and multiple respectively corresponding data buffers. A memory controller routes data traffic through available data interfaces for maximum bandwidth. In some circumstances, the memory controller directs the data I/O chip to de-activate one or more of the data interfaces (for example, to reduce power consumption). All subsequent data traffic to and from the memory module is routed through the remaining active interfaces. All physical addresses in the 3DS memory module are addressable through the remaining active interfaces. In some circumstances, the memory controller directs the data I/O chip to re-activate some or all of the de-activated data interfaces. Once re-activated, subsequent data traffic to and from the memory module can again be routed through all active interfaces.

公开(公告)号：US20180095884A1

公开(公告)日：2018-04-05

申请号：US15282478

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Maciej KAMINSKI ,  Piotr WYSOCKI ,  Slawomir PTAK

IPC: G06F12/0873 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0868

CPC classification number: G06F12/0873 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/068 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/1024 ,  G06F2212/205 ,  G06F2212/221 ,  G06F2212/2228 ,  G06F2212/224 ,  G06F2212/271 ,  G06F2212/284 ,  G06F2212/3042 ,  G06F2212/305 ,  G06F2212/313

Abstract: An apparatus is described. The apparatus includes a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of a system memory. The non volatile region of the system memory is to support execution of program code directly out of the non volatile region system memory.

公开(公告)号：US09927975B2

公开(公告)日：2018-03-27

申请号：US15227165

申请日：2016-08-03

Applicant: Micron Technology, Inc.

Inventor： Thomas L. Pratt

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0873 ,  G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/0605 ,  G06F3/0634 ,  G06F3/068 ,  G06F12/0246 ,  G06F12/0873 ,  G06F2212/217 ,  G06F2212/222 ,  G06F2212/261 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/313

Abstract: A multi-mode hybrid memory drive comprises a bulk memory device and a removable cache memory device. A controller of the bulk memory device may be configured to operate the bulk memory device in either a stand-alone mode or a hybrid mode responsive to detecting the removable cache memory device being coupled with a cache port of the bulk memory device. A method of operating a multi-mode hybrid drive may also comprise monitoring a cache port of a bulk memory device to determine a presence of a removable cache memory device, operating the bulk memory device as a stand-alone drive responsive to determining the removable cache memory device is not present, and operating the bulk memory device as a hybrid drive using the removable cache memory device as a data cache responsive to determining the removable cache memory device is present. Additional hybrid memory drives and computer systems are also described.

公开(公告)号：US20180032429A1

公开(公告)日：2018-02-01

申请号：US15224134

申请日：2016-07-29

Applicant: Intel Corporation

Inventor： Min LIU ,  Zhenlin LUO ,  George VERGIS ,  Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR ,  Ross E. ZWISLER

IPC: G06F12/02 ,  G06F12/0873 ,  G06F12/0871 ,  G06F12/084 ,  G06F12/0842

CPC classification number: G06F12/023 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/202 ,  G06F2212/205 ,  G06F2212/222 ,  G06F2212/225 ,  G06F2212/271 ,  G06F2212/305 ,  G06F2212/604

Abstract: A method is described. The method includes recognizing different latencies and/or bandwidths between different levels of a system memory and different memory access requestors of a computing system. The system memory includes the different levels and different technologies. The method also includes allocating each of the memory access requestors with a respective region of the system memory having an appropriate latency and/or bandwidth.

公开(公告)号：US20170132136A1

公开(公告)日：2017-05-11

申请号：US15216059

申请日：2016-07-21

Applicant: Microsoft Technology Licensing, LLC

Inventor： Cenk Ergan ,  Clark D. Nicholson ,  Daniel Teodosiu ,  Dean L. DeWhitt ,  Emily Nicole Wilson ,  Hanumantha R. Kodavalla ,  Michael J. Zwilling ,  John M. Parchem ,  Michael R. Fortin ,  Nathan Steven Obr ,  Rajeev Y. Nagar ,  Surenda Verma ,  Therron Powell ,  William J. Westerinen ,  Mark Joseph Zbikowski ,  Patrick L. Stemen

IPC: G06F12/0866 ,  G06F3/06

CPC classification number: G06F12/0866 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/08 ,  G06F2212/1016 ,  G06F2212/222 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/312 ,  G06F2212/313 ,  Y02D10/13

Abstract: In order to provide a more efficient persistent storage device, one or more long-term storage media are included along with a non-volatile memory. In one embodiment, one portion of the non-volatile memory is used as a write buffer and a read cache for writes and reads to the long-term storage media. Interfaces are provided for controlling the use of the non-volatile memory as a write buffer and a read cache. Additionally, a portion of the non-volatile memory is used to provide a direct mapping for specified sectors of the long-term storage media. Descriptive data regarding the persistent storage device is stored in another portion of the non-volatile memory.

公开(公告)号：US20170046260A1

公开(公告)日：2017-02-16

申请号：US14962524

申请日：2015-12-08

Applicant: Kabushiki Kaisha Toshiba

Inventor： Michihiko Umeda ,  Yusuke Izumizawa ,  Nobuhiro Sugawara ,  Seiji Toda

IPC: G06F12/08 ,  G06F11/14 ,  G06F3/06

CPC classification number: G06F12/0804 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/068 ,  G06F9/461 ,  G06F9/5022 ,  G06F11/1402 ,  G06F11/1446 ,  G06F12/0848 ,  G06F12/0868 ,  G06F2201/805 ,  G06F2212/1024 ,  G06F2212/1032 ,  G06F2212/222 ,  G06F2212/284 ,  G06F2212/3042 ,  G06F2212/305 ,  G06F2212/312 ,  G06F2212/401 ,  G06F2212/601

Abstract: According to one embodiment, a storage device includes a nonvolatile storage medium, a volatile memory and a controller. The volatile memory includes a cache area and a cache management area. The cache area is used to store, as write cache data, write data to be written to a user data area of the nonvolatile storage medium. The cache management area is used to store management information associated with the write cache data and including a compression size for the write cache data. The compression size is calculated in accordance with reception of a write command. The controller compresses, based on the management information, write cache data which is not saved to a save area and is needed to be compressed, and writes the compressed write cache data to the save area.

Abstract translation: 根据一个实施例，存储设备包括非易失性存储介质，易失性存储器和控制器。 易失性存储器包括高速缓存区域和高速缓存管理区域。 高速缓存区用于作为写入高速缓存数据存储要写入非易失性存储介质的用户数据区的数据。 高速缓存管理区域用于存储与写高速缓存数据相关联的管理信息，并且包括用于写高速缓存数据的压缩大小。 按照写命令的接收来计算压缩大小。 控制器基于管理信息压缩未保存到存储区域并需要压缩的高速缓存数据，并将压缩的写入高速缓存数据写入保存区域。