公开(公告)号：US12254926B2

公开(公告)日：2025-03-18

申请号：US17817288

申请日：2022-08-03

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Juane Li ,  Sead Zildzic, Jr. ,  Zhenming Zhou

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.

公开(公告)号：US12224017B2

公开(公告)日：2025-02-11

申请号：US17942977

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Paing Z. Htet ,  Sead Zildzic, Jr. ,  Thomas Fiala ,  Jian Huang ,  Zhenming Zhou

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26

Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.

公开(公告)号：US12272408B2

公开(公告)日：2025-04-08

申请号：US18138489

申请日：2023-04-24

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Paing Z. Htet ,  Sead Zildzic, Jr. ,  Thomas Fiala

IPC: G11C7/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed; adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.

公开(公告)号：US12242722B2

公开(公告)日：2025-03-04

申请号：US18221141

申请日：2023-07-12

Applicant: Micron Technology, Inc.

Inventor： Tomer Eliash ,  Sead Zildzic, Jr.

IPC: G06F3/06

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to store data according to a second memory storage process instead of a first memory storage process based on an underfill threshold.