公开(公告)号：US20250124987A1

公开(公告)日：2025-04-17

申请号：US18990013

申请日：2024-12-20

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Paing Z. Htet ,  Sead Zildzic, JR. ,  Thomas Fiala ,  Jian Huang ,  Zhenming Zhou

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/16

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations, including: determining a read voltage offset corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells.

公开(公告)号：US12224017B2

公开(公告)日：2025-02-11

申请号：US17942977

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Paing Z. Htet ,  Sead Zildzic, Jr. ,  Thomas Fiala ,  Jian Huang ,  Zhenming Zhou

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26

Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.

公开(公告)号：US20240087655A1

公开(公告)日：2024-03-14

申请号：US17942977

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Paing Z. Htet ,  Sead Zildzic, JR. ,  Thomas Fiala ,  Jian Huang ,  Zhenming Zhou

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/16

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/16

Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.

公开(公告)号：US12272408B2

公开(公告)日：2025-04-08

申请号：US18138489

申请日：2023-04-24

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Paing Z. Htet ,  Sead Zildzic, Jr. ,  Thomas Fiala

IPC: G11C7/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed; adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.

公开(公告)号：US20230368845A1

公开(公告)日：2023-11-16

申请号：US18138489

申请日：2023-04-24

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Paing Z. Htet ,  Sead Zildzic, JR. ,  Thomas Fiala

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/102

Abstract: A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed; adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.