公开(公告)号：US20240302885A1

公开(公告)日：2024-09-12

申请号：US18667548

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Tao Xiong ,  Guang Chng Ye ,  Jizhe Xing ,  Jun Shen

IPC: G06F1/3234 ,  G06F1/3225 ,  G11C5/14

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C5/14 ,  G11C2207/2227

Abstract: Various embodiments described herein provide for a method for reduced power consumption by a memory system. A memory system of some embodiments monitors power state change requests received by the memory system from a host system, and determines a pattern of power state change requests received from the host system. Based on the determined pattern, the memory system can decide to activate or deactivate a reduced power consumption mode on the memory system. A reduced power consumption mode can comprise a first set of operation parameters that cause a memory system to operate with lower power consumption than a second set of operation parameters associated with a current operation mode, where the current operation mode is associated with a current power state set or last requested by the host system.

公开(公告)号：US11288198B2

公开(公告)日：2022-03-29

申请号：US15733358

申请日：2019-12-23

Applicant: Micron Technology, Inc.

Inventor： Meng Wei ,  Shi Bo Zhang ,  Tao Xiong

IPC: G06F12/0891 ,  G06F12/0846 ,  G06F12/14 ,  G06F12/02

Abstract: A system includes a line cache, a memory device, and a processing device to execute firmware to detect that a received event is located in an events list, wherein events stored in the events list are associated with critical functions that occur no more than once per a threshold number of days and time out after between 15 microseconds and a predetermined number of hundreds of seconds. The firmware is further to enable access to the line cache and execute a critical function associated with the received event out of an always-loaded area of the line cache.

公开(公告)号：US11734184B2

公开(公告)日：2023-08-22

申请号：US17687103

申请日：2022-03-04

Applicant: Micron Technology, Inc.

Inventor： Meng Wei ,  Shi Bo Zhang ,  Tao Xiong

IPC: G06F12/0891 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/14

CPC classification number: G06F12/0891 ,  G06F12/0238 ,  G06F12/0848 ,  G06F12/1458 ,  G06F2212/1021

Abstract: A system includes a line cache, a memory device, and a processing device operatively coupled to the line cache and the memory device, The processing device includes a buffer manager and a high-speed mode driver, the processing device to perform operations including: detecting that a received event is located in an events list, wherein events stored in the events list are associated with a set of functions that are known to cause a clock domain crossing between the buffer manager and a host system; enabling access to the line cache; and running, using the high-speed mode driver, in a high-speed mode to execute the set of functions out of the line cache on behalf of the host system.

公开(公告)号：US12019497B2

公开(公告)日：2024-06-25

申请号：US17272055

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Tao Xiong ,  Guang Chang Ye ,  Jizhe Xing ,  Jun Shen

IPC: G06F1/3234 ,  G06F1/3225 ,  G11C5/14

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C5/14 ,  G11C2207/2227

Abstract: Various embodiments described herein provide for a method for reduced power consumption by a memory system. A memory system of some embodiments monitors power state change requests received by the memory system from a host system, and determines a pattern of power state change requests received from the host system. Based on the determined pattern, the memory system can decide to activate or deactivate a reduced power consumption mode on the memory system. A reduced power consumption mode can comprise a first set of operation parameters that cause a memory system to operate with lower power consumption than a second set of operation parameters associated with a current operation mode, where the current operation mode is associated with a current power state set or last requested by the host system.

公开(公告)号：US20230350482A1

公开(公告)日：2023-11-02

申请号：US17272055

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Tao Xiong ,  Guang Chang Ye ,  Jizhe Xing ,  Jun Shen

IPC: G06F1/3234 ,  G06F1/3225 ,  G11C5/14

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C5/14 ,  G11C2207/2227

Abstract: Various embodiments described herein provide for a method for reduced power consumption by a memory system. A memory system of some embodiments monitors power state change requests received by the memory system from a host system, and determines a pattern of power state change requests received from the host system. Based on the determined pattern, the memory system can decide to activate or deactivate a reduced power consumption mode on the memory system. A reduced power consumption mode can comprise a first set of operation parameters that cause a memory system to operate with lower power consumption than a second set of operation parameters associated with a current operation mode, where the current operation mode is associated with a current power state set or last requested by the host system.