公开(公告)号：US20230298951A1

公开(公告)日：2023-09-21

申请号：US17696261

申请日：2022-03-16

Applicant: Micron Technology, Inc.

Inventor： Chase M. Hunter ,  Marlon W. Hug ,  Stephen W. Russell ,  Rajesh Kamana ,  Amitava Majumdar ,  Radhakrishna Kotti ,  Ahmed N. Noemaun ,  Tejaswi K. Indukuri

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L22/32 ,  H01L22/12

Abstract: Test structures for wafers are disclosed. A device may include a silicon wafer including a number of die and a scribe area between two die of the number of die. The scribe area may include one or more test structures. The test structures may include a p-doped region and an n-doped region adjacent to the p-doped region. The test structures may also include a first contact electrically coupled to the p-doped region and a second contact electrically coupled to the n-doped region. The second contact may be proximate to the first contact. Associated devices, systems, and methods are also disclosed.