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公开(公告)号：US20240347107A1
公开(公告)日：2024-10-17
申请号：US18616989
申请日：2024-03-26
IPC分类号： G11C13/00 , H01L23/522 , H01L23/528 , H10B63/00 , H10N70/00 , H10N70/20
CPC分类号： G11C13/0028 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , H01L23/5226 , H01L23/528 , H10B63/84 , H10N70/231 , H10N70/826 , G11C2213/52 , G11C2213/71 , H10N70/841 , H10N70/8825
摘要： Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.
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公开(公告)号：US12019516B2
公开(公告)日：2024-06-25
申请号：US17894886
申请日：2022-08-24
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/0659 , G06F3/0689 , G06F11/1096
摘要： Provided is a memory system comprising a plurality of memory channels each having a parity bit, a redundant array of independent devices (RAID) parity channel, and a controller of the memory system. The controller is configured to receive a block of data for storage in the memory channels and determine at least one of (i) when a data traffic demand on the memory channels is high and (ii) when a data traffic demand on the memory channels is low. Upon determining the data traffic demand is low, writing the block of data for storage in the memory channels and concurrently updating the parity bits and the RAID parity channel for the stored block of data. Upon determining the data traffic demand is high, only writing the data for storage in the memory channels.
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公开(公告)号：US20240096438A1
公开(公告)日：2024-03-21
申请号：US18169610
申请日：2023-02-15
发明人： Amitava Majumdar , Greg S. Hendrix , Anandhavel Nagendrakumar , Krunal Patel , Kirthi Shenoy , Danilo Caraccio , Ankush Lal , Frank F. Ross , Adam D. Gailey
CPC分类号： G11C29/52 , G11C29/76 , G11C29/789
摘要： In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.
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公开(公告)号：US20240036762A1
公开(公告)日：2024-02-01
申请号：US18227216
申请日：2023-07-27
发明人： Edmund J. Gieske , Cagdas Dirik , Elliott C. Cooper-Balis , Robert M. Walker , Amitava Majumdar , Sujeet Ayyapureddi , Yang Lu , Ameen D. Akel , Niccolò Izzo , Danilo Caraccio , Markus H. Geiger
IPC分类号： G06F3/06 , G06F12/0802
CPC分类号： G06F3/0656 , G06F3/0604 , G06F3/0673 , G06F12/0802 , G06F2212/60
摘要： Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.
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公开(公告)号：US20230238049A1
公开(公告)日：2023-07-27
申请号：US17844450
申请日：2022-06-20
IPC分类号： G11C11/408 , G11C11/4094 , G11C11/4096 , G06F12/02 , G06F11/10
CPC分类号： G11C11/4085 , G11C11/4094 , G11C11/4096 , G06F12/0238 , G06F11/1068 , G06F2212/7201
摘要： Provided is a memory system including a memory module bank comprising a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells arranged in wordlines and bitlines and a memory controller configured to receive from a central processing unit (CPU) a data byte to be stored in a wordline of the memory module bank. Also included is a logical-to-physical address mapping block (L2P AMB) configured to map a logical bitline address of the data byte to a physical bitline address of a first memory cell array of the plurality of memory cell arrays, wherein a plurality of logical bitline addresses of the data byte are shuffled to different physical bitline memory addresses of the first memory cell array. Each respective memory cell array of the plurality stores a respective bit value, corresponding to a common logical bitline address, to a different respective physical bitline in each different respective memory cell array of the plurality.
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公开(公告)号：US20230195623A1
公开(公告)日：2023-06-22
申请号：US17556862
申请日：2021-12-20
发明人： Amitava Majumdar , Sandeep Krishna Thirumala , Lingming Yang , Karthik Sarpatwari , Nevil N. Gajera
IPC分类号： G06F12/0802
CPC分类号： G06F12/0802 , G06F2212/72 , G06F2212/60
摘要： This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.
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公开(公告)号：US11568952B2
公开(公告)日：2023-01-31
申请号：US17337195
申请日：2021-06-02
摘要： Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.
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公开(公告)号：US20220392526A1
公开(公告)日：2022-12-08
申请号：US17337806
申请日：2021-06-03
发明人： Lingming Yang , Xuan Anh Tran , Karthik Sarpatwari , Francesco Douglas Verna-Ketel , Jessica Chen , Nevil N. Gajera , Amitava Majumdar
摘要： Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.
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公开(公告)号：US20220301946A1
公开(公告)日：2022-09-22
申请号：US17714770
申请日：2022-04-06
IPC分类号： H01L21/66 , H01L21/768 , H01L27/24 , H01J37/28 , H01L23/528
摘要： Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.
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公开(公告)号：US20210151105A1
公开(公告)日：2021-05-20
申请号：US16685349
申请日：2019-11-15
IPC分类号： G11C13/00 , H01L23/528 , H01L23/522 , H01L27/24 , H01L45/00
摘要： Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.
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