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公开(公告)号：US20240312521A1
公开(公告)日：2024-09-19
申请号：US18593671
申请日：2024-03-01
CPC分类号： G11C16/0483 , H10B43/10 , H10B43/20
摘要： Methods, systems, and devices for trench and multiple pier architecture for three-dimensional memory arrays are described. Manufacturing operations for a memory device may include forming trenches, and subsequently forming multiple types of pier structures extending between the trenches in a first horizontal direction, in a second horizontal direction or both. For example, the trenches may be arranged in a grid-like structure extending in one or more rows and one or more columns. A set of a first type of pier may be formed along each of the trenches, a set of a second type of pier may be formed between adjacent trenches in the first horizontal direction, and a set of a third type of pier may be formed between adjacent trenches in the second horizontal direction.
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公开(公告)号：US20240185892A1
公开(公告)日：2024-06-06
申请号：US18525136
申请日：2023-11-30
摘要： Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.
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公开(公告)号：US11903223B2
公开(公告)日：2024-02-13
申请号：US17332640
申请日：2021-05-27
IPC分类号： H10B99/00 , H01L29/786 , H01L29/66 , H01L29/423 , H01L29/417 , H01L29/40 , H01L21/311 , G11C8/10 , G11C8/12 , H01L21/027 , H10B53/20 , H10B53/40 , H10B63/00
CPC分类号： H10B99/00 , H01L29/401 , H01L29/41733 , H01L29/41741 , H01L29/42384 , H01L29/66742 , H01L29/78642 , H01L29/78696 , G11C8/10 , G11C8/12 , H01L21/0274 , H01L21/31111 , H01L21/31144 , H10B53/20 , H10B53/40 , H10B63/84
摘要： Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.
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公开(公告)号：US20230309326A1
公开(公告)日：2023-09-28
申请号：US17656287
申请日：2022-03-24
CPC分类号： H01L27/249 , H01L45/1683
摘要： Methods, systems, and devices for dense piers for three-dimensional memory arrays are described. In some examples, a memory device may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate. For example, a memory device may include alternating layers of a first material and a second material. In some examples, the alternating layers may be formed into a pair of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns, and may provide mechanical support of cross-sectional pattern of the remaining material. In some examples, the piers may further act as a separator between memory cells or other features of the memory device. For example, the piers may extend into at least a portion of the interleaved comb structures, and may accordingly act as barriers during subsequent depositions of materials.
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公开(公告)号：US11706934B2
公开(公告)日：2023-07-18
申请号：US17174027
申请日：2021-02-11
IPC分类号： H01L27/24 , H01L27/11514 , H01L45/00 , H01L23/522 , H01L21/768
CPC分类号： H01L27/249 , H01L27/11514 , H01L21/76816 , H01L23/5226 , H01L45/065 , H01L45/085 , H01L45/16 , H01L45/1683
摘要： Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
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公开(公告)号：US11417841B2
公开(公告)日：2022-08-16
申请号：US16539932
申请日：2019-08-13
发明人： Stephen W. Russell , Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer , Lorenzo Fratin
摘要： Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.
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公开(公告)号：US10818324B2
公开(公告)日：2020-10-27
申请号：US16223632
申请日：2018-12-18
IPC分类号： G11C5/06 , H01L27/105 , G11C8/10 , H01L23/50
摘要： Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.
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公开(公告)号：US20190326356A1
公开(公告)日：2019-10-24
申请号：US15961540
申请日：2018-04-24
IPC分类号： H01L27/24 , H01L27/11514
摘要： Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
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公开(公告)号：US20190013358A1
公开(公告)日：2019-01-10
申请号：US16045514
申请日：2018-07-25
CPC分类号： H01L27/2463 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C13/0097 , H01L27/24 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
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10.发明申请公开(公告)号：US20160260777A1
公开(公告)日：2016-09-08
申请号：US15155433
申请日：2016-05-16
CPC分类号： H01L27/2472 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed.
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