公开(公告)号：US10338997B2

公开(公告)日：2019-07-02

申请号：US15983073

申请日：2018-05-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chiaki Dono ,  Seiichi Maruno ,  Taihei Shido ,  Toshio Ninomiya ,  Chikara Kondo

IPC: H03M13/00 ,  G06F11/10

Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.

公开(公告)号：US20160034340A1

公开(公告)日：2016-02-04

申请号：US14678375

申请日：2015-04-03

Applicant: Micron Technology, Inc.

Inventor： CHIAKI DONO ,  Seiichi Maruno ,  Taihei Shido ,  Toshio Ninomiya ,  Chikara Kondo

IPC: G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/1016

Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit, The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and as data bus invasion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.

Abstract translation: 一种装置包括第一外部终端，第一电路，信号线和第二电路。第一外部终端接收数据掩码信息和数据总线反转信息中的至少一个。 第一个电路执行错误检查操作和数据总线入侵操作之一。 信号线耦合在第一外部端子和第一电路之间。 第二电路耦合到信号线，并且首先响应于第一控制信号，以基本上恒定的电平将信号线的电压电平耦合。

公开(公告)号：US20180293128A1

公开(公告)日：2018-10-11

申请号：US15983073

申请日：2018-05-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chiaki Dono ,  Seiichi Maruno ,  Taihei Shido ,  Toshio Ninomiya ,  Chikara Kondo

IPC: G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/1016

Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the fist external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.

公开(公告)号：US09983925B2

公开(公告)日：2018-05-29

申请号：US14678375

申请日：2015-04-03

Applicant: Micron Technology, Inc.

Inventor： Chiaki Dono ,  Seiichi Maruno ,  Taihei Shido ,  Toshio Ninomiya ,  Chikara Kondo

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/1016

Abstract: A control circuit receives the mode signals supplied from a mode register and a read enable signal READ supplied from a control logic circuit, which activates enable signals EN1 to EN3 based on the mode signals and read enable signal. For example, the read enable signal READ is activated when a read command is issued from the controller. One mode signal can indicate an operation mode in which a multi-purpose register is used, and another mode signal can indicate an operation mode in which the data bus inversion function is used. When a data masking operation is disabled and an error check operation is enabled, the mode register activates a protection signal SEL. When the data masking operation is enabled or the error check operation is disabled, the protection signal SEL is deactivated. The operation of a deserializer is controlled by clock signals and the protection signal SEL.