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公开(公告)号：US20210104293A1
公开(公告)日：2021-04-08
申请号：US17124169
申请日：2020-12-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Chiaki Dono , Chikara Kondo , Roman A. Royer
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.
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公开(公告)号：US10937518B2
公开(公告)日：2021-03-02
申请号：US16218267
申请日：2018-12-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Roman A. Royer , Chikara Kondo , Chiaki Dono
Abstract: Apparatuses including a test interface circuit that is configured to merge multiple independent traffic streams generated from individual algorithmic pattern generators (APGs) for communication with a memory device over a shared memory interface. The combination of multiple independent traffic streams, each with their own looping sequences and command timings, may generate a large set of random command sequences. The test interface circuit may include an arbiter circuit that merges a first independent traffic stream from a first APG and a second independent traffic stream from a second APG. Each of the first and second independent traffic streams are directed to different semi-independently-accessible portions of the memory device. The memory device may include a hybrid memory cube having independently accessible vaults or a high bandwidth memory device having independently accessible channels, in some examples. The test interface circuit may be included in a built-in self-test engine or in a standalone tester.
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公开(公告)号：US10163469B2
公开(公告)日：2018-12-25
申请号：US15365563
申请日：2016-11-30
Applicant: Micron Technology, Inc.
Inventor： Chikara Kondo , Tomoyuki Shibata , Chiaki Dono , Seiji Narui , Minehiko Uehara , Taihei Shido , Homare Sato
Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.
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公开(公告)号：US11156658B2
公开(公告)日：2021-10-26
申请号：US16447409
申请日：2019-06-20
Applicant: Micron Technology, Inc.
Inventor： Chiaki Dono
Abstract: Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data terminal of a first channel of the memory apparatus from a memory array of the first channel via a first data path, receiving during a first test mode, first test information at the data terminal of the first channel from a first additional data path coupling the first channel with a second channel of the memory apparatus, and wherein an interface die of the memory apparatus includes the first data path and the additional data path.
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公开(公告)号：US10896738B1
公开(公告)日：2021-01-19
申请号：US16590694
申请日：2019-10-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Chiaki Dono , Chikara Kondo , Roman A. Royer
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.
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Patent Agency Ranking
公开(公告)号：US20190302181A1
公开(公告)日：2019-10-03
申请号：US16447409
申请日：2019-06-20
Applicant: Micron Technology, Inc.
Inventor： Chiaki Dono
IPC: G01R31/317 , G11C29/12 , G11C29/02
Abstract: Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data terminal of a first channel of the memory apparatus from a memory array of the first channel via a first data path, receiving during a first test mode, first test information at the data terminal of the first channel from a first additional data path coupling the first channel with a second channel of the memory apparatus, and wherein an interface die of the memory apparatus includes the first data path and the additional data path.
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公开(公告)号：US10373657B2
公开(公告)日：2019-08-06
申请号：US15233821
申请日：2016-08-10
Applicant: Micron Technology, Inc.
Inventor： Chikara Kondo , Chiaki Dono
Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.
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公开(公告)号：US10338997B2
公开(公告)日：2019-07-02
申请号：US15983073
申请日：2018-05-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Chiaki Dono , Seiichi Maruno , Taihei Shido , Toshio Ninomiya , Chikara Kondo
Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.
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公开(公告)号：US20190066816A1
公开(公告)日：2019-02-28
申请号：US15683430
申请日：2017-08-22
Applicant: Micron Technology, Inc.
Inventor： Chiaki Dono
CPC classification number: G01R31/31716 , G11C29/022 , G11C29/1201 , G11C29/36 , G11C29/38 , G11C29/48 , G11C2029/0401 , G11C2029/5602
Abstract: Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data terminal of a first channel of the memory apparatus from a memory array of the first channel via a first data path, receiving during a first test mode, first test information at the data terminal of the first channel from a first additional data path coupling the first channel with a second channel of the memory apparatus, and wherein an interface die of the memory apparatus includes the first data path and the additional data path.
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公开(公告)号：US20180047432A1
公开(公告)日：2018-02-15
申请号：US15233821
申请日：2016-08-10
Applicant: Micron Technology, Inc.
Inventor： Chikara Kondo , Chiaki Dono
CPC classification number: G11C7/1006 , G06F13/4282 , G11C5/025 , G11C5/066 , G11C7/1066 , G11C7/1093 , G11C7/222 , Y02D10/14 , Y02D10/151
Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.
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