公开(公告)号：US20240332229A1

公开(公告)日：2024-10-03

申请号：US18619071

申请日：2024-03-27

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Tzu Ching Hung ,  Kyle K. Kirby ,  Julia VanWinkle ,  Kyle B. Campbell ,  Bret K. Street

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/06517 ,  H01L2224/08146

Abstract: A semiconductor device is provided. The semiconductor device can have a front side at which circuitry is disposed. The circuitry can include a pad and a plurality of lines. A first layer of dielectric material can be disposed at the front side at least partially over the pad and the plurality of lines. A second layer of dielectric material can be disposed at the front side at least partially over the first layer of dielectric material. A dual damascene pad can extend through the first layer of dielectric material and the second layer of dielectric material to the pad. A dummy pad can be disposed in the second layer of dielectric material above the plurality of lines and spaced from the dual damascene pad. In doing so, a reliable semiconductor device can be implemented.

公开(公告)号：US12068282B2

公开(公告)日：2024-08-20

申请号：US17405673

申请日：2021-08-18

Applicant: Micron Technology, Inc.

Inventor： Tzu Ching Hung ,  Chien Wen Huang

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/76877 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/14 ,  H01L24/73

Abstract: A stacked semiconductor device having hybrid metallic structures and associated systems and methods are disclosed herein. The stacked semiconductor device can include a first semiconductor die and a second semiconductor die. The first semiconductor die can include a top surface, a first bond site at the top surface and a second bond site at the first surface spaced apart from the first bond site. The second semiconductor die can include a lower surface facing the top surface of the first semiconductor die, a third bond site at the lower surface, and a fourth bond site at the lower surface. The third bond site includes a conductive structure bonded to the first bond site by a metal-metal bond. The fourth bond site at the lower surface includes a solder ball bonded to the second bond site.

公开(公告)号：US20230055854A1

公开(公告)日：2023-02-23

申请号：US17405673

申请日：2021-08-18

Applicant: Micron Technology, Inc.

Inventor： Tzu Ching Hung ,  Chien Wen Huang

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768

Abstract: A stacked semiconductor device having hybrid metallic structures and associated systems and methods are disclosed herein. The stacked semiconductor device can include a first semiconductor die and a second semiconductor die. The first semiconductor die can include a top surface, a first bond site at the top surface and a second bond site at the first surface spaced apart from the first bond site. The second semiconductor die can include a lower surface facing the top surface of the first semiconductor die, a third bond site at the lower surface, and a fourth bond site at the lower surface. The third bond site includes a conductive structure bonded to the first bond site by a metal-metal bond. The fourth bond site at the lower surface includes a solder ball bonded to the second bond site.