公开(公告)号：US20240379176A1

公开(公告)日：2024-11-14

申请号：US18781317

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Shyam Sunder Raghunathan ,  Haiou Che ,  Walter di Francesco

IPC: G11C16/34 ,  G11C16/16

Abstract: Described are systems and methods for performing partial block erase operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined program state; determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.

公开(公告)号：US12087372B2

公开(公告)日：2024-09-10

申请号：US17845394

申请日：2022-06-21

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Shyam Sunder Raghunathan ,  Haiou Che ,  Walter di Francesco

IPC: G11C16/16 ,  G11C16/34

CPC classification number: G11C16/3445 ,  G11C16/16

Abstract: Described are systems and methods for performing partial block erase operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined program state; determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.

公开(公告)号：US20220415414A1

公开(公告)日：2022-12-29

申请号：US17845394

申请日：2022-06-21

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Shyam Sunder Raghunathan ,  Haiou Che ,  Walter di Francesco

IPC: G11C16/34 ,  G11C16/16

Abstract: Described are systems and methods for performing partial block erase operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined program state; determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.