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公开(公告)号：US20240312529A1
公开(公告)日：2024-09-19
申请号：US18602960
申请日：2024-03-12
CPC分类号： G11C16/26 , G11C16/0433 , G11C16/08
摘要： Control logic in a memory device receives a request to perform a corrective read operation on one or more memory cells associated with a selected wordline of a memory array of a memory device and determines whether one or more memory cells associated with an adjacent wordline of the memory array are in an erased state. Responsive to determining that the one or more memory cells associated with the adjacent wordline are in the erased state, the control logic identifies a partial block read voltage offset value and causes a read voltage modified according to the partial block read voltage offset value to be applied to the selected wordline to perform the corrective read operation on the one or more memory cells associated with the selected wordline.
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公开(公告)号：US20180190347A1
公开(公告)日：2018-07-05
申请号：US15907826
申请日：2018-02-28
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3427
摘要： Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.
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公开(公告)号：US20240168878A1
公开(公告)日：2024-05-23
申请号：US18386746
申请日：2023-11-03
发明人： Akira Goda , Kishore K. Muchherla , Shyam Sunder Raghunathan , Leo Raimondo , Jung Sheng Hoei , Xiangang Luo , Ashutosh Malshe , Jianmin Huang
IPC分类号： G06F12/02
CPC分类号： G06F12/0246
摘要： An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to: perform a programming operation on the first group of memory cells of the first erase block; monitor a quantity of programming and/or erase operations performed on the second group of memory cells subsequent to the programming of the first group of memory cells; and perform an action on the first erase block responsive to the quantity of programming and/or erase operations performed on the second group of memory cells meeting a criteria.
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公开(公告)号：US20220342813A1
公开(公告)日：2022-10-27
申请号：US17302064
申请日：2021-04-22
发明人： Kishore Kumar Muchherla , Giuseppina Puzzilli , Vamsi Pavan Rayaprolu , Ashutosh Malshe , James Fitzpatrick , Shyam Sunder Raghunathan , Violante Moschiano , Tecla Ghilardi
摘要： A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more low read disturb pages of the target wordline.
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公开(公告)号：US20240168879A1
公开(公告)日：2024-05-23
申请号：US18386760
申请日：2023-11-03
发明人： Akira Goda , Kishore K. Muchherla , Shyam Sunder Raghunathan , Leo Raimondo , Jung Sheng Hoei , Xiangang Luo , Ashutosh Malshe , Jianmin Huang
IPC分类号： G06F12/02
CPC分类号： G06F12/0246
摘要： An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.
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公开(公告)号：US20230197169A1
公开(公告)日：2023-06-22
申请号：US18083304
申请日：2022-12-16
CPC分类号： G11C16/32 , G11C16/102 , G11C16/08
摘要： A memory device includes an array of memory cells arranged in sub-blocks. Memory cells of a sub-block are coupled to a pillar of the array and are associated with multiple wordlines. To perform a read operation, control logic coupled with the array performs operations including: tracking a length of time that a selected wordline takes to reach a pass voltage before being able to read data from a memory cell associated with the selected wordline; in response to the length of time satisfying a first threshold criterion, causing a first delay time to pass before reading the data; and in response to the length of time satisfying a second threshold criterion that is longer than the first threshold criterion, causing a second delay time to pass before reading the data, the second delay time being longer than the first delay time.
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公开(公告)号：US10043574B2
公开(公告)日：2018-08-07
申请号：US15907826
申请日：2018-02-28
摘要： Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.
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公开(公告)号：US09922704B2
公开(公告)日：2018-03-20
申请号：US15189178
申请日：2016-06-22
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3427
摘要： Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.
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公开(公告)号：US20240168880A1
公开(公告)日：2024-05-23
申请号：US18386783
申请日：2023-11-03
发明人： Akira Goda , Niccolo' Righetti , Shyam Sunder Raghunathan , Leo Raimondo , Kishore K. Muccherla
IPC分类号： G06F12/02
CPC分类号： G06F12/0246
摘要： An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. A controller is configured to monitor a cumulative amount of read disturb stress experienced by a first erase block by: maintaining a read disturb count corresponding to the first erase block; incrementing the read disturb count by a first amount responsive to read commands issued to addresses corresponding to the first erase block; incrementing the read disturb count by a read disturb scaling factor responsive to read commands issued to addresses corresponding to the second erase block; and incrementing the read disturb count by a program scaling factor responsive to program commands issued to addresses corresponding to the second erase block. The controller can perform an action on the first erase block responsive to the read disturb count exceeding a threshold value.
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公开(公告)号：US09396791B2
公开(公告)日：2016-07-19
申请号：US14334946
申请日：2014-07-18
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3427
摘要： Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal.
摘要翻译： 提供了用于编程具有多级通过信号的存储器的存储器和方法。 一种方法包括将选择要编程的存储器的单元编程为存储器的特定目标数据状态，使用程序干扰来编程选择要编程的存储器的单元，以在编程期间将目标数据状态低于特定目标数据状态 将存储器的单元选择为被编程到特定目标数据状态，以及将选择要编程的存储器的单元的通道电压提升到低于特定目标数据状态的目标数据状态。 升压可能包括使用多步通过信号。
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